| Message ID | 20180308171335.31595-1-chris@chris-wilson.co.uk (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 08/03/18 09:13, Chris Wilson wrote: > Exercise some new API that allows applications to request that > individual contexts are executed within a desired frequency range. > > v2: Split single/continuous set_freq subtests > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > Cc: Paneri, Praveen <praveen.paneri@intel.com> > Cc: Kamble, Sagar A <sagar.a.kamble@intel.com> > Cc: Antonio Argenziano <antonio.argenziano@intel.com> > --- > tests/Makefile.am | 1 + > tests/Makefile.sources | 1 + > tests/gem_ctx_freq.c | 604 +++++++++++++++++++++++++++++++++++++++++++++++++ > tests/meson.build | 1 + > 4 files changed, 607 insertions(+) > create mode 100644 tests/gem_ctx_freq.c > > +static void single(int fd, const struct intel_execution_engine *e) > +{ > + const unsigned int engine = e->exec_id | e->flags; > + uint32_t ctx = gem_context_create(fd); > + uint32_t min, max; > + double measured; > + igt_spin_t *spin; > + int pmu; > + > + get_freq(fd, ctx, &min, &max); > + igt_info("Min freq: %dMHz; Max freq: %dMHz\n", min, max); > + > + pmu = perf_i915_open(I915_PMU_REQUESTED_FREQUENCY); > + igt_require(pmu >= 0); > + > + for (uint32_t freq = min + 50; freq <= max; freq += 100) { Although it is done in the smoke test, it would be interesting if freq's values were a bit randomized. > + uint32_t cur, discard; > + > + set_freq(fd, ctx, freq, freq); > + get_freq(fd, ctx, &cur, &discard); igt_assert_eq(freq, cur)? > + > + gem_quiescent_gpu(fd); > + spin = __igt_spin_batch_new(fd, ctx, engine, 0); > + usleep(10000); I guess here we wait for the frequency changes to take effect, maybe a small comment would help. > + > + measured = measure_frequency(pmu, SAMPLE_PERIOD); > + igt_debugfs_dump(fd, "i915_rps_boost_info"); > + > + igt_spin_batch_free(fd, spin); > + igt_info("%s(single): Measured %.1fMHz, expected %dMhz\n", > + e->name, measured, cur); > + igt_assert(measured > cur - 100 && measured < cur + 100); > + } > + gem_quiescent_gpu(fd); > + > + close(pmu); > + gem_context_destroy(fd, ctx); > +} > + > + > +static void sandwich(int fd) > +{ > + uint32_t ctx = gem_context_create(fd); > + unsigned int engine; > + uint32_t min, max; > + igt_spin_t *spin; > + int pmu; > + > + pmu = perf_i915_open(I915_PMU_REQUESTED_FREQUENCY); > + igt_require(pmu >= 0); > + > + spin = igt_spin_batch_new(fd, ctx, 0, 0); > + get_freq(fd, ctx, &min, &max); > + set_freq(fd, ctx, min, min); > + for_each_physical_engine(fd, engine) { > + struct drm_i915_gem_exec_object2 obj = { > + .handle = spin->handle, > + }; > + struct drm_i915_gem_execbuffer2 eb = { > + .buffer_count = 1, > + .buffers_ptr = to_user_pointer(&obj), > + .flags = engine, > + .rsvd1 = ctx, > + }; > + uint32_t cur, discard; > + double measured; > + > + min += 50; > + if (min > max) > + break; > + > + set_freq(fd, ctx, min, min); > + get_freq(fd, ctx, &cur, &discard); > + > + gem_execbuf(fd, &eb); > + usleep(10000); > + > + measured = measure_frequency(pmu, SAMPLE_PERIOD); > + igt_debugfs_dump(fd, "i915_rps_boost_info"); > + > + igt_info("Measured %.1fMHz, expected %dMhz\n", measured, cur); > + igt_assert(measured > cur - 100 && measured < cur + 100); Does the frequency change after each execbuf? > + } > + igt_spin_batch_free(fd, spin); > + gem_quiescent_gpu(fd); > + > + gem_context_destroy(fd, ctx); > + close(pmu); > +} > + > +static void pwm(int fd, unsigned int *engines, unsigned int nengine, int link) > +{ > + uint32_t ctx[nengine]; > + > + fcntl(link, F_SETFL, fcntl(fd, F_GETFL) | O_NONBLOCK); > + > + for (unsigned int n = 0; n < nengine; n++) > + ctx[n] = gem_context_create(fd); > + > + do { > + igt_spin_t *spin; > + struct { > + uint32_t engine; > + uint32_t min; > + uint32_t max; > + } req; > + > + while (read(link, &req, sizeof(req)) > 0) { > + if ((req.engine | req.min | req.max) == 0) > + goto out; > + > + igt_assert(req.engine < nengine); > + set_freq(fd, ctx[req.engine], req.min, req.max); > + } > + > + /* Create a 20% load using busy spinners */ > + spin = __igt_spin_batch_new(fd, ctx[0], engines[0], 0); > + for (unsigned int n = 1; n < nengine; n++) { > + struct drm_i915_gem_exec_object2 obj = { > + .handle = spin->handle, > + }; > + struct drm_i915_gem_execbuffer2 eb = { > + .buffer_count = 1, > + .buffers_ptr = to_user_pointer(&obj), > + .flags = engines[n], > + .rsvd1 = ctx[n], > + }; > + gem_execbuf(fd, &eb); > + } > + usleep(100); > + igt_spin_batch_end(spin); > + > + do > + usleep(10); > + while (gem_bo_busy(fd, spin->handle)); > + igt_spin_batch_free(fd, spin); > + usleep(400); > + } while (1); > + > +out: > + for (unsigned int n = 0; n < nengine; n++) > + gem_context_destroy(fd, ctx[n]); > +} > + > +static void smoketest(int fd, int timeout) > +{ > + unsigned int engines[16]; use a macro instead of magic number 16. > + unsigned int nengine; > + unsigned int engine; > + uint32_t min[16], max[16]; > + int pmu, link[2]; > + > + get_freq(fd, 0, &min[0], &max[0]); > + > + nengine = 0; > + for_each_physical_engine(fd, engine) { > + if (nengine == ARRAY_SIZE(engines) - 1) > + break; > + > + min[nengine] = min[0]; > + max[nengine] = max[0]; > + engines[nengine] = engine; > + nengine++; > + } > + igt_require(nengine); > + > + igt_assert(pipe(link) == 0); > + igt_fork(child, 1) > + pwm(fd, engines, nengine, link[0]); > + close(link[0]); > + > + pmu = perf_i915_open(I915_PMU_REQUESTED_FREQUENCY); > + igt_require(pmu >= 0); > + > + igt_until_timeout(timeout) { > + struct { > + uint32_t engine; > + uint32_t min; > + uint32_t max; > + } req; > + double measured; > + uint32_t ctx; > + > + req.engine = rand() % nengine; > + > + ctx = gem_context_create(fd); > + get_freq(fd, ctx, &req.min, &req.max); > + req.min = rand() % (req.max - req.min) + req.min; > + req.max = rand() % (req.max - req.min) + req.min; > + set_freq(fd, ctx, req.min, req.max); > + get_freq(fd, ctx, &req.min, &req.max); > + > + igt_debug("Replacing (%d, %d) on engine %x with (%d, %d)\n", > + min[req.engine], max[req.engine], req.engine, > + req.min, req.max); > + igt_assert(write(link[1], &req, sizeof(req)) == sizeof(req)); > + gem_context_destroy(fd, ctx); > + > + min[req.engine] = req.min; > + max[req.engine] = req.max; > + > + for (unsigned int n = 0; n < nengine; n++) { > + igt_debug("[%d]: [%d, %d]\n", n, min[n], max[n]); > + if (min[n] < req.min) > + req.min = min[n]; > + if (max[n] > req.max) > + req.max = max[n]; > + } > + igt_assert(req.max >= req.min); > + > + usleep(50000); > + measured = measure_frequency(pmu, SAMPLE_PERIOD); > + > + if (measured <= req.min - 100 || measured >= req.max + 100) > + igt_debugfs_dump(fd, "i915_rps_boost_info"); > + igt_info("Measured %.1fMHz, expected [%d, %d]Mhz\n", > + measured, req.min, req.max); > + igt_assert(measured > req.min - 100 && > + measured < req.max + 100); > + } > + > + do { > + struct { > + uint32_t engine; > + uint32_t min; > + uint32_t max; > + } req = {}; > + > + write(link[1], &req, sizeof(req)); > + close(link[1]); > + } while (0); > + igt_waitchildren(); > + gem_quiescent_gpu(fd); > + > + close(pmu); > +} > + > +static void invalid_param(int fd) > +{ gem_ctx_param is going to be upset again pretty soon ;). > + uint32_t min, max; > + uint32_t cur_min, cur_max; > + > + get_freq(fd, 0, &min, &max); > + > + igt_assert_eq(__set_freq(fd, 0, min - 50, max), -EINVAL); > + igt_assert_eq(__set_freq(fd, 0, min, max + 50), -EINVAL); One more case is both are out of boundary. igt_assert_eq(__set_freq(fd, 0, min - 50, max + 50), -EINVAL); > + igt_assert_eq(__set_freq(fd, 0, min + 50, min), -EINVAL); > + igt_assert_eq(__set_freq(fd, 0, max, max - 50), -EINVAL); > + > + get_freq(fd, 0, &cur_min, &cur_max); > + igt_assert_eq(cur_min, min); > + igt_assert_eq(cur_max, max); Check frequency didn't change after each ioctl. Thanks, Antonio
Quoting Antonio Argenziano (2018-03-09 00:45:42) > > > On 08/03/18 09:13, Chris Wilson wrote: > > Exercise some new API that allows applications to request that > > individual contexts are executed within a desired frequency range. > > > > v2: Split single/continuous set_freq subtests > > > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > > Cc: Paneri, Praveen <praveen.paneri@intel.com> > > Cc: Kamble, Sagar A <sagar.a.kamble@intel.com> > > Cc: Antonio Argenziano <antonio.argenziano@intel.com> > > --- > > tests/Makefile.am | 1 + > > tests/Makefile.sources | 1 + > > tests/gem_ctx_freq.c | 604 +++++++++++++++++++++++++++++++++++++++++++++++++ > > tests/meson.build | 1 + > > 4 files changed, 607 insertions(+) > > create mode 100644 tests/gem_ctx_freq.c > > > > > +static void single(int fd, const struct intel_execution_engine *e) > > +{ > > + const unsigned int engine = e->exec_id | e->flags; > > + uint32_t ctx = gem_context_create(fd); > > + uint32_t min, max; > > + double measured; > > + igt_spin_t *spin; > > + int pmu; > > + > > + get_freq(fd, ctx, &min, &max); > > + igt_info("Min freq: %dMHz; Max freq: %dMHz\n", min, max); > > + > > + pmu = perf_i915_open(I915_PMU_REQUESTED_FREQUENCY); > > + igt_require(pmu >= 0); > > + > > + for (uint32_t freq = min + 50; freq <= max; freq += 100) { > > Although it is done in the smoke test, it would be interesting if freq's > values were a bit randomized. It was intentionally increment only originally because the implementation was fast to upclock and slow to downclock. Given the challenge of the smoketest, I've shelved that laziness until it can pass that not particularly challenging test. I did have in mind doing an up/down ramp. We should also check that changing min while keeping max fixed should not affect a 100% load like the spinners. > > + uint32_t cur, discard; > > + > > + set_freq(fd, ctx, freq, freq); > > + get_freq(fd, ctx, &cur, &discard); > > igt_assert_eq(freq, cur)? Not quite. The trick is that the interface is not strictly idempotent, since we pass in MHz, the driver converts that into freq bins and spits it back out to the nearest MHz. So cur is not strictly freq, it just happens that 50MHz is the bin size on gen9. The idea here is that we grab the adjusted freq from the driver to validate with. > > + > > + gem_quiescent_gpu(fd); > > + spin = __igt_spin_batch_new(fd, ctx, engine, 0); > > + usleep(10000); > > I guess here we wait for the frequency changes to take effect, maybe a > small comment would help. And for the batch to be submitted. Asynchronous interfaces make it hard to pinpoint when things occur. We keep muttering about extending igt_spin_t to have an option for wait-for-exec (basically have it write out a dword that we can spin on) usleep(10000); /* wait for execution + freq change */ > > +static void sandwich(int fd) > > +{ > > + uint32_t ctx = gem_context_create(fd); > > + unsigned int engine; > > + uint32_t min, max; > > + igt_spin_t *spin; > > + int pmu; > > + > > + pmu = perf_i915_open(I915_PMU_REQUESTED_FREQUENCY); > > + igt_require(pmu >= 0); > > + > > + spin = igt_spin_batch_new(fd, ctx, 0, 0); > > + get_freq(fd, ctx, &min, &max); > > + set_freq(fd, ctx, min, min); > > + for_each_physical_engine(fd, engine) { > > + struct drm_i915_gem_exec_object2 obj = { > > + .handle = spin->handle, > > + }; > > + struct drm_i915_gem_execbuffer2 eb = { > > + .buffer_count = 1, > > + .buffers_ptr = to_user_pointer(&obj), > > + .flags = engine, > > + .rsvd1 = ctx, > > + }; > > + uint32_t cur, discard; > > + double measured; > > + > > + min += 50; > > + if (min > max) > > + break; > > + > > + set_freq(fd, ctx, min, min); > > + get_freq(fd, ctx, &cur, &discard); > > + > > + gem_execbuf(fd, &eb); > > + usleep(10000); > > + > > + measured = measure_frequency(pmu, SAMPLE_PERIOD); > > + igt_debugfs_dump(fd, "i915_rps_boost_info"); > > + > > + igt_info("Measured %.1fMHz, expected %dMhz\n", measured, cur); > > + igt_assert(measured > cur - 100 && measured < cur + 100); > > Does the frequency change after each execbuf? Yes. This turned into just an exercise across engines, bumping the desired freq. I wanted to try and validate the min/max bounds, but ran into the challenge that the gpu is only running at the highest frequency it can get because of the busy spinner :) > > +static void smoketest(int fd, int timeout) > > +{ > > + unsigned int engines[16]; > > use a macro instead of magic number 16. #define THIS_IS_FAR_MORE_MAGIC_THAN_A_MEANINGLESS_BARE_NUMBER_THAT_YOU_SHOULD_NOT_BE_READING_ANYTHING_INTO 16 /rant > > +static void invalid_param(int fd) > > +{ > > gem_ctx_param is going to be upset again pretty soon ;). Poor thing. -Chris
On 08/03/18 17:03, Chris Wilson wrote: > Quoting Antonio Argenziano (2018-03-09 00:45:42) >> >> >> On 08/03/18 09:13, Chris Wilson wrote: >>> Exercise some new API that allows applications to request that >>> individual contexts are executed within a desired frequency range. >>> >>> v2: Split single/continuous set_freq subtests >>> >>> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> >>> Cc: Paneri, Praveen <praveen.paneri@intel.com> >>> Cc: Kamble, Sagar A <sagar.a.kamble@intel.com> >>> Cc: Antonio Argenziano <antonio.argenziano@intel.com> >>> --- >>> tests/Makefile.am | 1 + >>> tests/Makefile.sources | 1 + >>> tests/gem_ctx_freq.c | 604 +++++++++++++++++++++++++++++++++++++++++++++++++ >>> tests/meson.build | 1 + >>> 4 files changed, 607 insertions(+) >>> create mode 100644 tests/gem_ctx_freq.c >>> >> >>> + uint32_t cur, discard; >>> + >>> + set_freq(fd, ctx, freq, freq); >>> + get_freq(fd, ctx, &cur, &discard); >> >> igt_assert_eq(freq, cur)? > > Not quite. The trick is that the interface is not strictly idempotent, > since we pass in MHz, the driver converts that into freq bins and spits > it back out to the nearest MHz. So cur is not strictly freq, it just > happens that 50MHz is the bin size on gen9. > > The idea here is that we grab the adjusted freq from the driver to > validate with. I see, can we enforce a tolerance? It feels like we are trusting the kernel too much, but if that is the only thing we can do... >>> +static void smoketest(int fd, int timeout) >>> +{ >>> + unsigned int engines[16]; >> >> use a macro instead of magic number 16. > > #define THIS_IS_FAR_MORE_MAGIC_THAN_A_MEANINGLESS_BARE_NUMBER_THAT_YOU_SHOULD_NOT_BE_READING_ANYTHING_INTO 16 > /rant We call that MAX_EGINES in gem_exec_schedule ;). Thanks, Antonio > >>> +static void invalid_param(int fd) >>> +{ >> >> gem_ctx_param is going to be upset again pretty soon ;). > > Poor thing. > -Chris >
Quoting Antonio Argenziano (2018-03-09 19:15:45) > > > On 08/03/18 17:03, Chris Wilson wrote: > > Quoting Antonio Argenziano (2018-03-09 00:45:42) > >> > >> > >> On 08/03/18 09:13, Chris Wilson wrote: > >>> Exercise some new API that allows applications to request that > >>> individual contexts are executed within a desired frequency range. > >>> > >>> v2: Split single/continuous set_freq subtests > >>> > >>> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > >>> Cc: Paneri, Praveen <praveen.paneri@intel.com> > >>> Cc: Kamble, Sagar A <sagar.a.kamble@intel.com> > >>> Cc: Antonio Argenziano <antonio.argenziano@intel.com> > >>> --- > >>> tests/Makefile.am | 1 + > >>> tests/Makefile.sources | 1 + > >>> tests/gem_ctx_freq.c | 604 +++++++++++++++++++++++++++++++++++++++++++++++++ > >>> tests/meson.build | 1 + > >>> 4 files changed, 607 insertions(+) > >>> create mode 100644 tests/gem_ctx_freq.c > >>> > >> > > >>> + uint32_t cur, discard; > >>> + > >>> + set_freq(fd, ctx, freq, freq); > >>> + get_freq(fd, ctx, &cur, &discard); > >> > >> igt_assert_eq(freq, cur)? > > > > Not quite. The trick is that the interface is not strictly idempotent, > > since we pass in MHz, the driver converts that into freq bins and spits > > it back out to the nearest MHz. So cur is not strictly freq, it just > > happens that 50MHz is the bin size on gen9. > > > > The idea here is that we grab the adjusted freq from the driver to > > validate with. > > I see, can we enforce a tolerance? It feels like we are trusting the > kernel too much, but if that is the only thing we can do... for (i = min; i <= max; i++) igt_assert(min <= set_and_fetch_freq(i) <= max); I don't think we want to constrain the ABI any more than that. But adding that level of check seems ok. The behaviour is we ask the kernel for a range, the kernel tells us what range it can provide based on the request. Then we expect that the kernel upholds that contract. (Except where we make a conflicting contract with another party, either parallel execution or sysadmin override.) Binding ourselves into a tighter contract feels overly prescriptive and not flexible enough to weasel our way out of bad situations in future. -Chris
diff --git a/tests/Makefile.am b/tests/Makefile.am index dbc7be72..389f7fc7 100644 --- a/tests/Makefile.am +++ b/tests/Makefile.am @@ -104,6 +104,7 @@ drm_import_export_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS) drm_import_export_LDADD = $(LDADD) -lpthread gem_close_race_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS) gem_close_race_LDADD = $(LDADD) -lpthread +gem_ctx_freq_LDADD = $(LDADD) $(top_builddir)/lib/libigt_perf.la gem_ctx_thrash_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS) gem_ctx_thrash_LDADD = $(LDADD) -lpthread gem_exec_parallel_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS) diff --git a/tests/Makefile.sources b/tests/Makefile.sources index 4a81ac4a..3d079c42 100644 --- a/tests/Makefile.sources +++ b/tests/Makefile.sources @@ -58,6 +58,7 @@ TESTS_progs = \ gem_ctx_bad_exec \ gem_ctx_create \ gem_ctx_exec \ + gem_ctx_freq \ gem_ctx_isolation \ gem_ctx_param \ gem_ctx_switch \ diff --git a/tests/gem_ctx_freq.c b/tests/gem_ctx_freq.c new file mode 100644 index 00000000..f7e79ac3 --- /dev/null +++ b/tests/gem_ctx_freq.c @@ -0,0 +1,604 @@ +/* + * Copyright © 2018 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + */ + +#include <unistd.h> +#include <stdlib.h> +#include <stdint.h> +#include <stdio.h> +#include <string.h> +#include <fcntl.h> +#include <inttypes.h> +#include <errno.h> +#include <sys/stat.h> +#include <sys/ioctl.h> +#include <sys/time.h> +#include <time.h> + +#include "igt.h" +#include "igt_perf.h" + +#define LOCAL_CONTEXT_PARAM_FREQUENCY 8 + +#define SAMPLE_PERIOD (USEC_PER_SEC / 10) + +static int __set_freq(int fd, uint32_t ctx, uint32_t min, uint32_t max) +{ + struct drm_i915_gem_context_param param = { + .ctx_id = ctx, + .param = LOCAL_CONTEXT_PARAM_FREQUENCY, + .value = (uint64_t)max << 32 | min, + }; + + return __gem_context_set_param(fd, ¶m); +} + +static void set_freq(int fd, uint32_t ctx, uint32_t min, uint32_t max) +{ + igt_assert_eq(__set_freq(fd, ctx, min, max), 0); +} + +static void get_freq(int fd, uint32_t ctx, uint32_t *min, uint32_t *max) +{ + struct drm_i915_gem_context_param param = { + .ctx_id = ctx, + .param = LOCAL_CONTEXT_PARAM_FREQUENCY, + }; + + gem_context_get_param(fd, ¶m); + + *min = param.value & 0xffffffff; + *max = param.value >> 32; +} + +static double measure_frequency(int pmu, int period_us) +{ + uint64_t data[2]; + uint64_t d_t, d_v; + + igt_assert_eq(read(pmu, data, sizeof(data)), sizeof(data)); + d_v = -data[0]; + d_t = -data[1]; + + usleep(period_us); + + igt_assert_eq(read(pmu, data, sizeof(data)), sizeof(data)); + d_v += data[0]; + d_t += data[1]; + + return d_v * 1e9 / d_t; +} + +static void single(int fd, const struct intel_execution_engine *e) +{ + const unsigned int engine = e->exec_id | e->flags; + uint32_t ctx = gem_context_create(fd); + uint32_t min, max; + double measured; + igt_spin_t *spin; + int pmu; + + get_freq(fd, ctx, &min, &max); + igt_info("Min freq: %dMHz; Max freq: %dMHz\n", min, max); + + pmu = perf_i915_open(I915_PMU_REQUESTED_FREQUENCY); + igt_require(pmu >= 0); + + for (uint32_t freq = min + 50; freq <= max; freq += 100) { + uint32_t cur, discard; + + set_freq(fd, ctx, freq, freq); + get_freq(fd, ctx, &cur, &discard); + + gem_quiescent_gpu(fd); + spin = __igt_spin_batch_new(fd, ctx, engine, 0); + usleep(10000); + + measured = measure_frequency(pmu, SAMPLE_PERIOD); + igt_debugfs_dump(fd, "i915_rps_boost_info"); + + igt_spin_batch_free(fd, spin); + igt_info("%s(single): Measured %.1fMHz, expected %dMhz\n", + e->name, measured, cur); + igt_assert(measured > cur - 100 && measured < cur + 100); + } + gem_quiescent_gpu(fd); + + close(pmu); + gem_context_destroy(fd, ctx); +} + +static void continuous(int fd, const struct intel_execution_engine *e) +{ + const unsigned int engine = e->exec_id | e->flags; + uint32_t ctx = gem_context_create(fd); + uint32_t min, max; + double measured; + igt_spin_t *spin; + int pmu; + + get_freq(fd, ctx, &min, &max); + igt_info("Min freq: %dMHz; Max freq: %dMHz\n", min, max); + + pmu = perf_i915_open(I915_PMU_REQUESTED_FREQUENCY); + igt_require(pmu >= 0); + + gem_quiescent_gpu(fd); + spin = __igt_spin_batch_new(fd, ctx, engine, 0); + for (uint32_t freq = min + 50; freq <= max; freq += 100) { + uint32_t cur, discard; + igt_spin_t *kick; + + set_freq(fd, ctx, freq, freq); + get_freq(fd, ctx, &cur, &discard); + + /* + * When requesting a new frequency on the currently + * executing context, it does not take effect until the + * next context switch. In this case, we trigger a lite + * restore. + */ + kick = __igt_spin_batch_new(fd, ctx, engine, 0); + igt_spin_batch_free(fd, spin); + spin = kick; + + usleep(10000); + + measured = measure_frequency(pmu, SAMPLE_PERIOD); + igt_debugfs_dump(fd, "i915_rps_boost_info"); + + igt_info("%s(continuous): Measured %.1fMHz, expected %dMhz\n", + e->name, measured, cur); + igt_assert(measured > cur - 100 && measured < cur + 100); + } + igt_spin_batch_free(fd, spin); + gem_quiescent_gpu(fd); + + close(pmu); + gem_context_destroy(fd, ctx); +} + +static void inflight(int fd, const struct intel_execution_engine *e) +{ + const unsigned int engine = e->exec_id | e->flags; + uint32_t ctx, min, max, freq, discard; + double measured; + igt_spin_t *plug, *work[2]; + int pmu; + + pmu = perf_i915_open(I915_PMU_REQUESTED_FREQUENCY); + igt_require(pmu >= 0); + + ctx = gem_context_create(fd); + get_freq(fd, ctx, &min, &max); + set_freq(fd, ctx, min, min); + + igt_info("Min freq: %dMHz; Max freq: %dMHz\n", min, max); + + gem_quiescent_gpu(fd); + plug = igt_spin_batch_new(fd, ctx, engine, 0); + gem_context_destroy(fd, ctx); + for (int n = 0; n < 16; n++) { + struct drm_i915_gem_exec_object2 obj = { + .handle = plug->handle, + }; + struct drm_i915_gem_execbuffer2 eb = { + .buffer_count = 1, + .buffers_ptr = to_user_pointer(&obj), + .flags = engine, + .rsvd1 = gem_context_create(fd), + }; + set_freq(fd, eb.rsvd1, min, min); + gem_execbuf(fd, &eb); + gem_context_destroy(fd, eb.rsvd1); + } + measured = measure_frequency(pmu, SAMPLE_PERIOD); + igt_debugfs_dump(fd, "i915_rps_boost_info"); + igt_info("%s(plug): Measured %.1fMHz, expected %dMhz\n", + e->name, measured, min); + igt_assert(measured > min - 100 && measured < min + 100); + + ctx = gem_context_create(fd); + set_freq(fd, ctx, max, max); + work[0] = __igt_spin_batch_new(fd, ctx, engine, 0); + + /* work is now queued but not executing */ + freq = (max + min) / 2; + set_freq(fd, ctx, freq, freq); + get_freq(fd, ctx, &freq, &discard); + gem_context_destroy(fd, ctx); + + ctx = gem_context_create(fd); + set_freq(fd, ctx, max, max); + work[1] = __igt_spin_batch_new(fd, ctx, engine, 0); + gem_context_destroy(fd, ctx); + + igt_spin_batch_end(plug); + do + usleep(10000); + while (gem_bo_busy(fd, plug->handle)); + igt_spin_batch_free(fd, plug); + + /* Now work will execute */ + measured = measure_frequency(pmu, SAMPLE_PERIOD); + igt_debugfs_dump(fd, "i915_engine_info"); + igt_debugfs_dump(fd, "i915_rps_boost_info"); + igt_info("%s(work0): Measured %.1fMHz, expected %dMhz\n", + e->name, measured, freq); + igt_assert(measured > freq - 100 && measured < freq + 100); + + igt_spin_batch_end(work[0]); + do + usleep(10000); + while (gem_bo_busy(fd, work[0]->handle)); + igt_spin_batch_free(fd, work[0]); + + measured = measure_frequency(pmu, SAMPLE_PERIOD); + igt_debugfs_dump(fd, "i915_engine_info"); + igt_debugfs_dump(fd, "i915_rps_boost_info"); + igt_info("%s(work1): Measured %.1fMHz, expected %dMhz\n", + e->name, measured, max); + igt_assert(measured > max - 100 && measured < max + 100); + + igt_spin_batch_free(fd, work[1]); + close(pmu); + gem_quiescent_gpu(fd); +} + +static void sandwich(int fd) +{ + uint32_t ctx = gem_context_create(fd); + unsigned int engine; + uint32_t min, max; + igt_spin_t *spin; + int pmu; + + pmu = perf_i915_open(I915_PMU_REQUESTED_FREQUENCY); + igt_require(pmu >= 0); + + spin = igt_spin_batch_new(fd, ctx, 0, 0); + get_freq(fd, ctx, &min, &max); + set_freq(fd, ctx, min, min); + for_each_physical_engine(fd, engine) { + struct drm_i915_gem_exec_object2 obj = { + .handle = spin->handle, + }; + struct drm_i915_gem_execbuffer2 eb = { + .buffer_count = 1, + .buffers_ptr = to_user_pointer(&obj), + .flags = engine, + .rsvd1 = ctx, + }; + uint32_t cur, discard; + double measured; + + min += 50; + if (min > max) + break; + + set_freq(fd, ctx, min, min); + get_freq(fd, ctx, &cur, &discard); + + gem_execbuf(fd, &eb); + usleep(10000); + + measured = measure_frequency(pmu, SAMPLE_PERIOD); + igt_debugfs_dump(fd, "i915_rps_boost_info"); + + igt_info("Measured %.1fMHz, expected %dMhz\n", measured, cur); + igt_assert(measured > cur - 100 && measured < cur + 100); + } + igt_spin_batch_free(fd, spin); + gem_quiescent_gpu(fd); + + gem_context_destroy(fd, ctx); + close(pmu); +} + +static void pwm(int fd, unsigned int *engines, unsigned int nengine, int link) +{ + uint32_t ctx[nengine]; + + fcntl(link, F_SETFL, fcntl(fd, F_GETFL) | O_NONBLOCK); + + for (unsigned int n = 0; n < nengine; n++) + ctx[n] = gem_context_create(fd); + + do { + igt_spin_t *spin; + struct { + uint32_t engine; + uint32_t min; + uint32_t max; + } req; + + while (read(link, &req, sizeof(req)) > 0) { + if ((req.engine | req.min | req.max) == 0) + goto out; + + igt_assert(req.engine < nengine); + set_freq(fd, ctx[req.engine], req.min, req.max); + } + + /* Create a 20% load using busy spinners */ + spin = __igt_spin_batch_new(fd, ctx[0], engines[0], 0); + for (unsigned int n = 1; n < nengine; n++) { + struct drm_i915_gem_exec_object2 obj = { + .handle = spin->handle, + }; + struct drm_i915_gem_execbuffer2 eb = { + .buffer_count = 1, + .buffers_ptr = to_user_pointer(&obj), + .flags = engines[n], + .rsvd1 = ctx[n], + }; + gem_execbuf(fd, &eb); + } + usleep(100); + igt_spin_batch_end(spin); + + do + usleep(10); + while (gem_bo_busy(fd, spin->handle)); + igt_spin_batch_free(fd, spin); + usleep(400); + } while (1); + +out: + for (unsigned int n = 0; n < nengine; n++) + gem_context_destroy(fd, ctx[n]); +} + +static void smoketest(int fd, int timeout) +{ + unsigned int engines[16]; + unsigned int nengine; + unsigned int engine; + uint32_t min[16], max[16]; + int pmu, link[2]; + + get_freq(fd, 0, &min[0], &max[0]); + + nengine = 0; + for_each_physical_engine(fd, engine) { + if (nengine == ARRAY_SIZE(engines) - 1) + break; + + min[nengine] = min[0]; + max[nengine] = max[0]; + engines[nengine] = engine; + nengine++; + } + igt_require(nengine); + + igt_assert(pipe(link) == 0); + igt_fork(child, 1) + pwm(fd, engines, nengine, link[0]); + close(link[0]); + + pmu = perf_i915_open(I915_PMU_REQUESTED_FREQUENCY); + igt_require(pmu >= 0); + + igt_until_timeout(timeout) { + struct { + uint32_t engine; + uint32_t min; + uint32_t max; + } req; + double measured; + uint32_t ctx; + + req.engine = rand() % nengine; + + ctx = gem_context_create(fd); + get_freq(fd, ctx, &req.min, &req.max); + req.min = rand() % (req.max - req.min) + req.min; + req.max = rand() % (req.max - req.min) + req.min; + set_freq(fd, ctx, req.min, req.max); + get_freq(fd, ctx, &req.min, &req.max); + + igt_debug("Replacing (%d, %d) on engine %x with (%d, %d)\n", + min[req.engine], max[req.engine], req.engine, + req.min, req.max); + igt_assert(write(link[1], &req, sizeof(req)) == sizeof(req)); + gem_context_destroy(fd, ctx); + + min[req.engine] = req.min; + max[req.engine] = req.max; + + for (unsigned int n = 0; n < nengine; n++) { + igt_debug("[%d]: [%d, %d]\n", n, min[n], max[n]); + if (min[n] < req.min) + req.min = min[n]; + if (max[n] > req.max) + req.max = max[n]; + } + igt_assert(req.max >= req.min); + + usleep(50000); + measured = measure_frequency(pmu, SAMPLE_PERIOD); + + if (measured <= req.min - 100 || measured >= req.max + 100) + igt_debugfs_dump(fd, "i915_rps_boost_info"); + igt_info("Measured %.1fMHz, expected [%d, %d]Mhz\n", + measured, req.min, req.max); + igt_assert(measured > req.min - 100 && + measured < req.max + 100); + } + + do { + struct { + uint32_t engine; + uint32_t min; + uint32_t max; + } req = {}; + + write(link[1], &req, sizeof(req)); + close(link[1]); + } while (0); + igt_waitchildren(); + gem_quiescent_gpu(fd); + + close(pmu); +} + +static void invalid_param(int fd) +{ + uint32_t min, max; + uint32_t cur_min, cur_max; + + get_freq(fd, 0, &min, &max); + + igt_assert_eq(__set_freq(fd, 0, min - 50, max), -EINVAL); + igt_assert_eq(__set_freq(fd, 0, min, max + 50), -EINVAL); + igt_assert_eq(__set_freq(fd, 0, min + 50, min), -EINVAL); + igt_assert_eq(__set_freq(fd, 0, max, max - 50), -EINVAL); + + get_freq(fd, 0, &cur_min, &cur_max); + igt_assert_eq(cur_min, min); + igt_assert_eq(cur_max, max); +} + +static void idempotent(int fd) +{ + uint32_t min, max; + uint32_t cur_min, cur_max; + + get_freq(fd, 0, &min, &max); + + set_freq(fd, 0, max, max); + get_freq(fd, 0, &cur_min, &cur_max); + igt_assert_eq(cur_min, max); + igt_assert_eq(cur_max, max); + + set_freq(fd, 0, min, min); + get_freq(fd, 0, &cur_min, &cur_max); + igt_assert_eq(cur_min, min); + igt_assert_eq(cur_max, min); + + set_freq(fd, 0, min, max); + get_freq(fd, 0, &cur_min, &cur_max); + igt_assert_eq(cur_min, min); + igt_assert_eq(cur_max, max); +} + +static void independent(int fd) +{ + uint32_t min, max; + uint32_t cur_min, cur_max; + uint32_t ctx[2]; + + get_freq(fd, 0, &min, &max); + + set_freq(fd, 0, max, max); + ctx[0] = gem_context_create(fd); + get_freq(fd, ctx[0], &cur_min, &cur_max); + igt_assert_eq(cur_min, min); + igt_assert_eq(cur_max, max); + + set_freq(fd, 0, min, min); + get_freq(fd, ctx[0], &cur_min, &cur_max); + igt_assert_eq(cur_min, min); + igt_assert_eq(cur_max, max); + + ctx[1] = gem_context_create(fd); + get_freq(fd, ctx[1], &cur_min, &cur_max); + igt_assert_eq(cur_min, min); + igt_assert_eq(cur_max, max); + + set_freq(fd, ctx[1], max, max); + get_freq(fd, ctx[0], &cur_min, &cur_max); + igt_assert_eq(cur_min, min); + igt_assert_eq(cur_max, max); + + get_freq(fd, 0, &cur_min, &cur_max); + igt_assert_eq(cur_min, min); + igt_assert_eq(cur_max, min); + + get_freq(fd, ctx[1], &cur_min, &cur_max); + igt_assert_eq(cur_min, max); + igt_assert_eq(cur_max, max); + gem_context_destroy(fd, ctx[1]); + + get_freq(fd, ctx[0], &cur_min, &cur_max); + igt_assert_eq(cur_min, min); + igt_assert_eq(cur_max, max); + gem_context_destroy(fd, ctx[0]); +} + +static bool has_ctx_freq(int fd) +{ + struct drm_i915_gem_context_param param = { + .param = LOCAL_CONTEXT_PARAM_FREQUENCY, + }; + + return __gem_context_get_param(fd, ¶m) == 0; +} + +igt_main +{ + const struct intel_execution_engine *e; + int fd = -1; + + igt_fixture { + fd = drm_open_driver(DRIVER_INTEL); + igt_require_gem(fd); + + igt_require(has_ctx_freq(fd)); + } + + igt_subtest("invalid") + invalid_param(fd); + + igt_subtest("idempotent") + idempotent(fd); + + igt_subtest("independent") + independent(fd); + + igt_skip_on_simulation(); + + for (e = intel_execution_engines; e->name; e++) { + if (e->exec_id == 0) + continue; + + igt_subtest_group { + igt_fixture { + igt_require(gem_ring_has_physical_engine(fd, e->exec_id | e->flags)); + } + + igt_subtest_f("%s-single", e->name) + single(fd, e); + igt_subtest_f("%s-continuous", e->name) + continuous(fd, e); + igt_subtest_f("%s-inflight", e->name) + inflight(fd, e); + } + } + + igt_subtest("sandwich") + sandwich(fd); + + igt_subtest("smoketest") + smoketest(fd, 20); +} diff --git a/tests/meson.build b/tests/meson.build index 58729231..f1271274 100644 --- a/tests/meson.build +++ b/tests/meson.build @@ -35,6 +35,7 @@ test_progs = [ 'gem_ctx_bad_exec', 'gem_ctx_create', 'gem_ctx_exec', + 'gem_ctx_freq', 'gem_ctx_param', 'gem_ctx_switch', 'gem_ctx_thrash',
Exercise some new API that allows applications to request that individual contexts are executed within a desired frequency range. v2: Split single/continuous set_freq subtests Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Paneri, Praveen <praveen.paneri@intel.com> Cc: Kamble, Sagar A <sagar.a.kamble@intel.com> Cc: Antonio Argenziano <antonio.argenziano@intel.com> --- tests/Makefile.am | 1 + tests/Makefile.sources | 1 + tests/gem_ctx_freq.c | 604 +++++++++++++++++++++++++++++++++++++++++++++++++ tests/meson.build | 1 + 4 files changed, 607 insertions(+) create mode 100644 tests/gem_ctx_freq.c