| Message ID | 1527103862-13934-5-git-send-email-jsanka@codeaurora.org (mailing list archive) |
|---|---|
| State | Superseded, archived |
| Delegated to: | Andy Gross |
| Headers | show |
On Wed, May 23, 2018 at 12:30:59PM -0700, Jeykumar Sankaran wrote: > Replace custom plane zpos property with drm core zpos > property. CRTC relies on the normalized zpos values > to configure blend stages of each plane. > > Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org> > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 36 +------------------------------ > drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 18 +++++++++++++--- > 2 files changed, 16 insertions(+), 38 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c > index d439a9e..a0b702f 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c > @@ -2631,24 +2631,6 @@ struct plane_state { > u32 pipe_id; > }; > > -static int pstate_cmp(const void *a, const void *b) > -{ > - struct plane_state *pa = (struct plane_state *)a; > - struct plane_state *pb = (struct plane_state *)b; > - int rc = 0; > - int pa_zpos, pb_zpos; > - > - pa_zpos = dpu_plane_get_property(pa->dpu_pstate, PLANE_PROP_ZPOS); > - pb_zpos = dpu_plane_get_property(pb->dpu_pstate, PLANE_PROP_ZPOS); > - > - if (pa_zpos != pb_zpos) > - rc = pa_zpos - pb_zpos; > - else > - rc = pa->drm_pstate->crtc_x - pb->drm_pstate->crtc_x; > - > - return rc; > -} > - > static int dpu_crtc_atomic_check(struct drm_crtc *crtc, > struct drm_crtc_state *state) > { > @@ -2714,8 +2696,7 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, > > pstates[cnt].dpu_pstate = to_dpu_plane_state(pstate); > pstates[cnt].drm_pstate = pstate; > - pstates[cnt].stage = dpu_plane_get_property( > - pstates[cnt].dpu_pstate, PLANE_PROP_ZPOS); > + pstates[cnt].stage = pstate->normalized_zpos; > pstates[cnt].pipe_id = dpu_plane_pipe(plane); > > /* check dim layer stage with every plane */ > @@ -2771,21 +2752,6 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, > } > } > > - /* assign mixer stages based on sorted zpos property */ > - sort(pstates, cnt, sizeof(pstates[0]), pstate_cmp, NULL); > - > - if (!dpu_is_custom_client()) { > - int stage_old = pstates[0].stage; > - > - z_pos = 0; > - for (i = 0; i < cnt; i++) { > - if (stage_old != pstates[i].stage) > - ++z_pos; > - stage_old = pstates[i].stage; > - pstates[i].stage = z_pos; > - } > - } > - > z_pos = -1; > for (i = 0; i < cnt; i++) { > /* reset counts at every new blend stage */ > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c > index b033653..28735c8 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c > @@ -59,6 +59,7 @@ > #define DPU_NAME_SIZE 12 > > #define DPU_PLANE_COLOR_FILL_FLAG BIT(31) > +#define DPU_ZPOS_MAX 255 > > /* multirect rect index */ > enum { > @@ -1518,9 +1519,6 @@ static void _dpu_plane_install_properties(struct drm_plane *plane, > /* reserve zpos == 0 for primary planes */ > zpos_def = drm_plane_index(plane) + 1; > } > - > - msm_property_install_range(&pdpu->property_info, "zpos", > - 0x0, 0, zpos_max, zpos_def, PLANE_PROP_ZPOS); > } > > static int dpu_plane_atomic_set_property(struct drm_plane *plane, > @@ -1958,6 +1956,7 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev, > struct msm_drm_private *priv; > struct dpu_kms *kms; > enum drm_plane_type type; > + int zpos_max = DPU_ZPOS_MAX; > int ret = -EINVAL; > > if (!dev) { > @@ -2049,6 +2048,19 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev, > if (ret) > goto clean_sspp; > > + pdpu->catalog = kms->catalog; > + > + if (kms->catalog->mixer_count && > + kms->catalog->mixer[0].sblk->maxblendstages) { > + zpos_max = kms->catalog->mixer[0].sblk->maxblendstages - 1; > + if (zpos_max > DPU_STAGE_MAX - DPU_STAGE_0 - 1) > + zpos_max = DPU_STAGE_MAX - DPU_STAGE_0 - 1; > + } > + > + ret = drm_plane_create_zpos_property(plane, 0, 0, zpos_max); > + if (ret) > + DPU_ERROR("failed to install zpos property, rc = %d\n", ret); > + drm_plane_create_zpos_property() can either return 0 or -ENOMEM so printing the return value isn't interesting. > /* success! finalize initialization */ > drm_plane_helper_add(plane, &dpu_plane_helper_funcs); > > -- > The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, > a Linux Foundation Collaborative Project > > _______________________________________________ > Freedreno mailing list > Freedreno@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/freedreno
On Wed, May 23, 2018 at 12:30:59PM -0700, Jeykumar Sankaran wrote: > Replace custom plane zpos property with drm core zpos > property. CRTC relies on the normalized zpos values > to configure blend stages of each plane. > > Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org> > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 36 +------------------------------ > drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 18 +++++++++++++--- > 2 files changed, 16 insertions(+), 38 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c > index d439a9e..a0b702f 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c > @@ -2631,24 +2631,6 @@ struct plane_state { > u32 pipe_id; > }; > > -static int pstate_cmp(const void *a, const void *b) > -{ > - struct plane_state *pa = (struct plane_state *)a; > - struct plane_state *pb = (struct plane_state *)b; > - int rc = 0; > - int pa_zpos, pb_zpos; > - > - pa_zpos = dpu_plane_get_property(pa->dpu_pstate, PLANE_PROP_ZPOS); > - pb_zpos = dpu_plane_get_property(pb->dpu_pstate, PLANE_PROP_ZPOS); > - > - if (pa_zpos != pb_zpos) > - rc = pa_zpos - pb_zpos; > - else > - rc = pa->drm_pstate->crtc_x - pb->drm_pstate->crtc_x; > - > - return rc; > -} > - > static int dpu_crtc_atomic_check(struct drm_crtc *crtc, > struct drm_crtc_state *state) > { > @@ -2714,8 +2696,7 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, > > pstates[cnt].dpu_pstate = to_dpu_plane_state(pstate); > pstates[cnt].drm_pstate = pstate; > - pstates[cnt].stage = dpu_plane_get_property( > - pstates[cnt].dpu_pstate, PLANE_PROP_ZPOS); > + pstates[cnt].stage = pstate->normalized_zpos; > pstates[cnt].pipe_id = dpu_plane_pipe(plane); > > /* check dim layer stage with every plane */ > @@ -2771,21 +2752,6 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, > } > } > > - /* assign mixer stages based on sorted zpos property */ > - sort(pstates, cnt, sizeof(pstates[0]), pstate_cmp, NULL); > - > - if (!dpu_is_custom_client()) { > - int stage_old = pstates[0].stage; > - > - z_pos = 0; > - for (i = 0; i < cnt; i++) { > - if (stage_old != pstates[i].stage) > - ++z_pos; > - stage_old = pstates[i].stage; > - pstates[i].stage = z_pos; > - } > - } > - > z_pos = -1; > for (i = 0; i < cnt; i++) { > /* reset counts at every new blend stage */ > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c > index b033653..28735c8 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c > @@ -59,6 +59,7 @@ > #define DPU_NAME_SIZE 12 > > #define DPU_PLANE_COLOR_FILL_FLAG BIT(31) > +#define DPU_ZPOS_MAX 255 > > /* multirect rect index */ > enum { > @@ -1518,9 +1519,6 @@ static void _dpu_plane_install_properties(struct drm_plane *plane, > /* reserve zpos == 0 for primary planes */ > zpos_def = drm_plane_index(plane) + 1; > } > - > - msm_property_install_range(&pdpu->property_info, "zpos", > - 0x0, 0, zpos_max, zpos_def, PLANE_PROP_ZPOS); > } > > static int dpu_plane_atomic_set_property(struct drm_plane *plane, > @@ -1958,6 +1956,7 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev, > struct msm_drm_private *priv; > struct dpu_kms *kms; > enum drm_plane_type type; > + int zpos_max = DPU_ZPOS_MAX; > int ret = -EINVAL; > > if (!dev) { > @@ -2049,6 +2048,19 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev, > if (ret) > goto clean_sspp; > > + pdpu->catalog = kms->catalog; > + Why is this here? It seems unrelated to the patch. > + if (kms->catalog->mixer_count && > + kms->catalog->mixer[0].sblk->maxblendstages) { > + zpos_max = kms->catalog->mixer[0].sblk->maxblendstages - 1; > + if (zpos_max > DPU_STAGE_MAX - DPU_STAGE_0 - 1) > + zpos_max = DPU_STAGE_MAX - DPU_STAGE_0 - 1; > + } > + > + ret = drm_plane_create_zpos_property(plane, 0, 0, zpos_max); > + if (ret) > + DPU_ERROR("failed to install zpos property, rc = %d\n", ret); > + > /* success! finalize initialization */ > drm_plane_helper_add(plane, &dpu_plane_helper_funcs); > > -- > The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, > a Linux Foundation Collaborative Project >
On Wed, May 23, 2018 at 03:21:15PM -0600, Jordan Crouse wrote: > On Wed, May 23, 2018 at 12:30:59PM -0700, Jeykumar Sankaran wrote: > > Replace custom plane zpos property with drm core zpos > > property. CRTC relies on the normalized zpos values > > to configure blend stages of each plane. > > > > Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org> > > --- > > drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 36 +------------------------------ > > drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 18 +++++++++++++--- > > 2 files changed, 16 insertions(+), 38 deletions(-) > > > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c > > index d439a9e..a0b702f 100644 > > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c > > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c > > @@ -2631,24 +2631,6 @@ struct plane_state { > > u32 pipe_id; > > }; > > > > -static int pstate_cmp(const void *a, const void *b) > > -{ > > - struct plane_state *pa = (struct plane_state *)a; > > - struct plane_state *pb = (struct plane_state *)b; > > - int rc = 0; > > - int pa_zpos, pb_zpos; > > - > > - pa_zpos = dpu_plane_get_property(pa->dpu_pstate, PLANE_PROP_ZPOS); > > - pb_zpos = dpu_plane_get_property(pb->dpu_pstate, PLANE_PROP_ZPOS); > > - > > - if (pa_zpos != pb_zpos) > > - rc = pa_zpos - pb_zpos; > > - else > > - rc = pa->drm_pstate->crtc_x - pb->drm_pstate->crtc_x; > > - > > - return rc; > > -} > > - > > static int dpu_crtc_atomic_check(struct drm_crtc *crtc, > > struct drm_crtc_state *state) > > { > > @@ -2714,8 +2696,7 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, > > > > pstates[cnt].dpu_pstate = to_dpu_plane_state(pstate); > > pstates[cnt].drm_pstate = pstate; > > - pstates[cnt].stage = dpu_plane_get_property( > > - pstates[cnt].dpu_pstate, PLANE_PROP_ZPOS); > > + pstates[cnt].stage = pstate->normalized_zpos; > > pstates[cnt].pipe_id = dpu_plane_pipe(plane); > > > > /* check dim layer stage with every plane */ > > @@ -2771,21 +2752,6 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, > > } > > } > > > > - /* assign mixer stages based on sorted zpos property */ > > - sort(pstates, cnt, sizeof(pstates[0]), pstate_cmp, NULL); > > - > > - if (!dpu_is_custom_client()) { > > - int stage_old = pstates[0].stage; > > - > > - z_pos = 0; > > - for (i = 0; i < cnt; i++) { > > - if (stage_old != pstates[i].stage) > > - ++z_pos; > > - stage_old = pstates[i].stage; > > - pstates[i].stage = z_pos; > > - } > > - } > > - > > z_pos = -1; > > for (i = 0; i < cnt; i++) { > > /* reset counts at every new blend stage */ > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c > > index b033653..28735c8 100644 > > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c > > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c > > @@ -59,6 +59,7 @@ > > #define DPU_NAME_SIZE 12 > > > > #define DPU_PLANE_COLOR_FILL_FLAG BIT(31) > > +#define DPU_ZPOS_MAX 255 > > > > /* multirect rect index */ > > enum { > > @@ -1518,9 +1519,6 @@ static void _dpu_plane_install_properties(struct drm_plane *plane, > > /* reserve zpos == 0 for primary planes */ > > zpos_def = drm_plane_index(plane) + 1; > > } > > - > > - msm_property_install_range(&pdpu->property_info, "zpos", > > - 0x0, 0, zpos_max, zpos_def, PLANE_PROP_ZPOS); > > } > > > > static int dpu_plane_atomic_set_property(struct drm_plane *plane, > > @@ -1958,6 +1956,7 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev, > > struct msm_drm_private *priv; > > struct dpu_kms *kms; > > enum drm_plane_type type; > > + int zpos_max = DPU_ZPOS_MAX; > > int ret = -EINVAL; > > > > if (!dev) { > > @@ -2049,6 +2048,19 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev, > > if (ret) > > goto clean_sspp; > > > > + pdpu->catalog = kms->catalog; > > + > > + if (kms->catalog->mixer_count && > > + kms->catalog->mixer[0].sblk->maxblendstages) { > > + zpos_max = kms->catalog->mixer[0].sblk->maxblendstages - 1; > > + if (zpos_max > DPU_STAGE_MAX - DPU_STAGE_0 - 1) > > + zpos_max = DPU_STAGE_MAX - DPU_STAGE_0 - 1; > > + } > > + > > + ret = drm_plane_create_zpos_property(plane, 0, 0, zpos_max); > > + if (ret) > > + DPU_ERROR("failed to install zpos property, rc = %d\n", ret); > > + > > drm_plane_create_zpos_property() can either return 0 or -ENOMEM This may not always be true. > so > printing the return value isn't interesting. Also if I was reviewing or casual reading this without the ret print, I would probably leave a comment such as "print the return value" since I don't generally keep track of all possible return values. So printing the return value seems reasonable to me. Sean > > > /* success! finalize initialization */ > > drm_plane_helper_add(plane, &dpu_plane_helper_funcs); > > > > -- > > The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, > > a Linux Foundation Collaborative Project > > > > _______________________________________________ > > Freedreno mailing list > > Freedreno@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/freedreno > > -- > The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, > a Linux Foundation Collaborative Project
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index d439a9e..a0b702f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -2631,24 +2631,6 @@ struct plane_state { u32 pipe_id; }; -static int pstate_cmp(const void *a, const void *b) -{ - struct plane_state *pa = (struct plane_state *)a; - struct plane_state *pb = (struct plane_state *)b; - int rc = 0; - int pa_zpos, pb_zpos; - - pa_zpos = dpu_plane_get_property(pa->dpu_pstate, PLANE_PROP_ZPOS); - pb_zpos = dpu_plane_get_property(pb->dpu_pstate, PLANE_PROP_ZPOS); - - if (pa_zpos != pb_zpos) - rc = pa_zpos - pb_zpos; - else - rc = pa->drm_pstate->crtc_x - pb->drm_pstate->crtc_x; - - return rc; -} - static int dpu_crtc_atomic_check(struct drm_crtc *crtc, struct drm_crtc_state *state) { @@ -2714,8 +2696,7 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, pstates[cnt].dpu_pstate = to_dpu_plane_state(pstate); pstates[cnt].drm_pstate = pstate; - pstates[cnt].stage = dpu_plane_get_property( - pstates[cnt].dpu_pstate, PLANE_PROP_ZPOS); + pstates[cnt].stage = pstate->normalized_zpos; pstates[cnt].pipe_id = dpu_plane_pipe(plane); /* check dim layer stage with every plane */ @@ -2771,21 +2752,6 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, } } - /* assign mixer stages based on sorted zpos property */ - sort(pstates, cnt, sizeof(pstates[0]), pstate_cmp, NULL); - - if (!dpu_is_custom_client()) { - int stage_old = pstates[0].stage; - - z_pos = 0; - for (i = 0; i < cnt; i++) { - if (stage_old != pstates[i].stage) - ++z_pos; - stage_old = pstates[i].stage; - pstates[i].stage = z_pos; - } - } - z_pos = -1; for (i = 0; i < cnt; i++) { /* reset counts at every new blend stage */ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index b033653..28735c8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -59,6 +59,7 @@ #define DPU_NAME_SIZE 12 #define DPU_PLANE_COLOR_FILL_FLAG BIT(31) +#define DPU_ZPOS_MAX 255 /* multirect rect index */ enum { @@ -1518,9 +1519,6 @@ static void _dpu_plane_install_properties(struct drm_plane *plane, /* reserve zpos == 0 for primary planes */ zpos_def = drm_plane_index(plane) + 1; } - - msm_property_install_range(&pdpu->property_info, "zpos", - 0x0, 0, zpos_max, zpos_def, PLANE_PROP_ZPOS); } static int dpu_plane_atomic_set_property(struct drm_plane *plane, @@ -1958,6 +1956,7 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev, struct msm_drm_private *priv; struct dpu_kms *kms; enum drm_plane_type type; + int zpos_max = DPU_ZPOS_MAX; int ret = -EINVAL; if (!dev) { @@ -2049,6 +2048,19 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev, if (ret) goto clean_sspp; + pdpu->catalog = kms->catalog; + + if (kms->catalog->mixer_count && + kms->catalog->mixer[0].sblk->maxblendstages) { + zpos_max = kms->catalog->mixer[0].sblk->maxblendstages - 1; + if (zpos_max > DPU_STAGE_MAX - DPU_STAGE_0 - 1) + zpos_max = DPU_STAGE_MAX - DPU_STAGE_0 - 1; + } + + ret = drm_plane_create_zpos_property(plane, 0, 0, zpos_max); + if (ret) + DPU_ERROR("failed to install zpos property, rc = %d\n", ret); + /* success! finalize initialization */ drm_plane_helper_add(plane, &dpu_plane_helper_funcs);
Replace custom plane zpos property with drm core zpos property. CRTC relies on the normalized zpos values to configure blend stages of each plane. Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org> --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 36 +------------------------------ drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 18 +++++++++++++--- 2 files changed, 16 insertions(+), 38 deletions(-)