| Message ID | 20181026051439.27032-1-anusha.srivatsa@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/fia: FIA registers offset implementation. | expand |
On Thu, Oct 25, 2018 at 10:14:39PM -0700, Anusha Srivatsa wrote: > The registers DPCSSS,DPSP,DPMLE1 and DPPMS are all at an offset > from the base - which is the FLexi IO Adaptor. Lets follow the > offset calculation while accessing these registers. > > Cc: Lucas De Marchi <lucas.demarchi@intel.com> > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 15 +++++++++++---- > 1 file changed, 11 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 69eb573348b3..e2f5c3a95ad4 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -2057,8 +2057,15 @@ enum i915_power_well_id { > #define BXT_PORT_CL2CM_DW6(phy) _BXT_PHY((phy), _PORT_CL2CM_DW6_BC) > #define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28) > > +/* FIA Offsets */ > +#define FIA_0 0x163000 spec and other registers start at 1, not 0. So for consistency I think you should change the name here to FIA_1, or even _FIA1 to follow what's done in other registers. Lucas De Marchi > +#define PORT_TX_DFLEXDPMLE1_OFFSET 0x008C0 > +#define PORT_TX_DFLEXDPPMS_OFFSET 0x00890 > +#define PORT_TX_DFLEXDPCSSS_OFFSET 0x00894 > +#define PORT_TX_DFLEXDPSP_OFFSET 0x008A0 > + > /* ICL PHY DFLEX registers */ > -#define PORT_TX_DFLEXDPMLE1 _MMIO(0x1638C0) > +#define PORT_TX_DFLEXDPMLE1 _MMIO(FIA_0 + PORT_TX_DFLEXDPMLE1_OFFSET) > #define DFLEXDPMLE1_DPMLETC_MASK(n) (0xf << (4 * (n))) > #define DFLEXDPMLE1_DPMLETC(n, x) ((x) << (4 * (n))) > > @@ -10957,17 +10964,17 @@ enum skl_power_gate { > _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB, \ > _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC) > > -#define PORT_TX_DFLEXDPSP _MMIO(0x1638A0) > +#define PORT_TX_DFLEXDPSP _MMIO(FIA_0 + PORT_TX_DFLEXDPSP_OFFSET) > #define TC_LIVE_STATE_TBT(tc_port) (1 << ((tc_port) * 8 + 6)) > #define TC_LIVE_STATE_TC(tc_port) (1 << ((tc_port) * 8 + 5)) > #define DP_LANE_ASSIGNMENT_SHIFT(tc_port) ((tc_port) * 8) > #define DP_LANE_ASSIGNMENT_MASK(tc_port) (0xf << ((tc_port) * 8)) > #define DP_LANE_ASSIGNMENT(tc_port, x) ((x) << ((tc_port) * 8)) > > -#define PORT_TX_DFLEXDPPMS _MMIO(0x163890) > +#define PORT_TX_DFLEXDPPMS _MMIO(FIA_0 + PORT_TX_DFLEXDPPMS_OFFSET) > #define DP_PHY_MODE_STATUS_COMPLETED(tc_port) (1 << (tc_port)) > > -#define PORT_TX_DFLEXDPCSSS _MMIO(0x163894) > +#define PORT_TX_DFLEXDPCSSS _MMIO(FIA_0 + PORT_TX_DFLEXDPCSSS_OFFSET) > #define DP_PHY_MODE_STATUS_NOT_SAFE(tc_port) (1 << (tc_port)) > > #endif /* _I915_REG_H_ */ > -- > 2.17.1 >
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 69eb573348b3..e2f5c3a95ad4 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2057,8 +2057,15 @@ enum i915_power_well_id { #define BXT_PORT_CL2CM_DW6(phy) _BXT_PHY((phy), _PORT_CL2CM_DW6_BC) #define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28) +/* FIA Offsets */ +#define FIA_0 0x163000 +#define PORT_TX_DFLEXDPMLE1_OFFSET 0x008C0 +#define PORT_TX_DFLEXDPPMS_OFFSET 0x00890 +#define PORT_TX_DFLEXDPCSSS_OFFSET 0x00894 +#define PORT_TX_DFLEXDPSP_OFFSET 0x008A0 + /* ICL PHY DFLEX registers */ -#define PORT_TX_DFLEXDPMLE1 _MMIO(0x1638C0) +#define PORT_TX_DFLEXDPMLE1 _MMIO(FIA_0 + PORT_TX_DFLEXDPMLE1_OFFSET) #define DFLEXDPMLE1_DPMLETC_MASK(n) (0xf << (4 * (n))) #define DFLEXDPMLE1_DPMLETC(n, x) ((x) << (4 * (n))) @@ -10957,17 +10964,17 @@ enum skl_power_gate { _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB, \ _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC) -#define PORT_TX_DFLEXDPSP _MMIO(0x1638A0) +#define PORT_TX_DFLEXDPSP _MMIO(FIA_0 + PORT_TX_DFLEXDPSP_OFFSET) #define TC_LIVE_STATE_TBT(tc_port) (1 << ((tc_port) * 8 + 6)) #define TC_LIVE_STATE_TC(tc_port) (1 << ((tc_port) * 8 + 5)) #define DP_LANE_ASSIGNMENT_SHIFT(tc_port) ((tc_port) * 8) #define DP_LANE_ASSIGNMENT_MASK(tc_port) (0xf << ((tc_port) * 8)) #define DP_LANE_ASSIGNMENT(tc_port, x) ((x) << ((tc_port) * 8)) -#define PORT_TX_DFLEXDPPMS _MMIO(0x163890) +#define PORT_TX_DFLEXDPPMS _MMIO(FIA_0 + PORT_TX_DFLEXDPPMS_OFFSET) #define DP_PHY_MODE_STATUS_COMPLETED(tc_port) (1 << (tc_port)) -#define PORT_TX_DFLEXDPCSSS _MMIO(0x163894) +#define PORT_TX_DFLEXDPCSSS _MMIO(FIA_0 + PORT_TX_DFLEXDPCSSS_OFFSET) #define DP_PHY_MODE_STATUS_NOT_SAFE(tc_port) (1 << (tc_port)) #endif /* _I915_REG_H_ */
The registers DPCSSS,DPSP,DPMLE1 and DPPMS are all at an offset from the base - which is the FLexi IO Adaptor. Lets follow the offset calculation while accessing these registers. Cc: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-)