| Message ID | 1548755647-23356-1-git-send-email-pillair@codeaurora.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | ath10k: Fix shadow register implementation for WCN3990 | expand |
Rakesh Pillai <pillair@codeaurora.org> wrote: > WCN3990 supports shadow registers write operation support > for copy engine for regular operation in powersave mode. > > Since WCN3990 is a 64-bit target, the shadow register > implementation needs to be done in the copy engine handlers > for 64-bit target. Currently the shadow register implementation > is present in the 32-bit target handlers of copy engine. > > Fix the shadow register copy engine write operation > implementation for 64-bit target(WCN3990). > > Tested HW: WCN3990 > Tested FW: WLAN.HL.2.0-01188-QCAHLSWMTPLZ-1 > > Fixes: b7ba83f7c414 ("ath10k: add support for shadow register for WNC3990") > Signed-off-by: Rakesh Pillai <pillair@codeaurora.org> > Signed-off-by: Kalle Valo <kvalo@codeaurora.org> I was able to apply with 3-way merge but please double check the results: https://git.kernel.org/pub/scm/linux/kernel/git/kvalo/ath.git/commit/?h=pending&id=45112636f48a180c2867c78731ea28ac665495d9 Applying: ath10k: Fix shadow register implementation for WCN3990 Using index info to reconstruct a base tree... M drivers/net/wireless/ath/ath10k/ce.c M drivers/net/wireless/ath/ath10k/ce.h Falling back to patching base and 3-way merge... Auto-merging drivers/net/wireless/ath/ath10k/ce.h Auto-merging drivers/net/wireless/ath/ath10k/ce.c
Hi Kalle, I have checked the patch, and it is fine. Thanks, Rakesh Pillai. On 2019-02-08 19:47, Kalle Valo wrote: > Rakesh Pillai <pillair@codeaurora.org> wrote: > >> WCN3990 supports shadow registers write operation support >> for copy engine for regular operation in powersave mode. >> >> Since WCN3990 is a 64-bit target, the shadow register >> implementation needs to be done in the copy engine handlers >> for 64-bit target. Currently the shadow register implementation >> is present in the 32-bit target handlers of copy engine. >> >> Fix the shadow register copy engine write operation >> implementation for 64-bit target(WCN3990). >> >> Tested HW: WCN3990 >> Tested FW: WLAN.HL.2.0-01188-QCAHLSWMTPLZ-1 >> >> Fixes: b7ba83f7c414 ("ath10k: add support for shadow register for >> WNC3990") >> Signed-off-by: Rakesh Pillai <pillair@codeaurora.org> >> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> > > I was able to apply with 3-way merge but please double check the > results: > > https://git.kernel.org/pub/scm/linux/kernel/git/kvalo/ath.git/commit/?h=pending&id=45112636f48a180c2867c78731ea28ac665495d9 > > Applying: ath10k: Fix shadow register implementation for WCN3990 > Using index info to reconstruct a base tree... > M drivers/net/wireless/ath/ath10k/ce.c > M drivers/net/wireless/ath/ath10k/ce.h > Falling back to patching base and 3-way merge... > Auto-merging drivers/net/wireless/ath/ath10k/ce.h > Auto-merging drivers/net/wireless/ath/ath10k/ce.c
Rakesh Pillai <pillair@codeaurora.org> wrote: > WCN3990 supports shadow registers write operation support > for copy engine for regular operation in powersave mode. > > Since WCN3990 is a 64-bit target, the shadow register > implementation needs to be done in the copy engine handlers > for 64-bit target. Currently the shadow register implementation > is present in the 32-bit target handlers of copy engine. > > Fix the shadow register copy engine write operation > implementation for 64-bit target(WCN3990). > > Tested HW: WCN3990 > Tested FW: WLAN.HL.2.0-01188-QCAHLSWMTPLZ-1 > > Fixes: b7ba83f7c414 ("ath10k: add support for shadow register for WNC3990") > Signed-off-by: Rakesh Pillai <pillair@codeaurora.org> > Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Patch applied to ath-next branch of ath.git, thanks. 1863008369ae ath10k: fix shadow register implementation for WCN3990
diff --git a/drivers/net/wireless/ath/ath10k/ce.c b/drivers/net/wireless/ath/ath10k/ce.c index f6d3ecb..31b9e46 100644 --- a/drivers/net/wireless/ath/ath10k/ce.c +++ b/drivers/net/wireless/ath/ath10k/ce.c @@ -500,14 +500,8 @@ static int _ath10k_ce_send_nolock(struct ath10k_ce_pipe *ce_state, write_index = CE_RING_IDX_INCR(nentries_mask, write_index); /* WORKAROUND */ - if (!(flags & CE_SEND_FLAG_GATHER)) { - if (ar->hw_params.shadow_reg_support) - ath10k_ce_shadow_src_ring_write_index_set(ar, ce_state, - write_index); - else - ath10k_ce_src_ring_write_index_set(ar, ctrl_addr, - write_index); - } + if (!(flags & CE_SEND_FLAG_GATHER)) + ath10k_ce_src_ring_write_index_set(ar, ctrl_addr, write_index); src_ring->write_index = write_index; exit: @@ -581,8 +575,14 @@ static int _ath10k_ce_send_nolock_64(struct ath10k_ce_pipe *ce_state, /* Update Source Ring Write Index */ write_index = CE_RING_IDX_INCR(nentries_mask, write_index); - if (!(flags & CE_SEND_FLAG_GATHER)) - ath10k_ce_src_ring_write_index_set(ar, ctrl_addr, write_index); + if (!(flags & CE_SEND_FLAG_GATHER)) { + if (ar->hw_params.shadow_reg_support) + ath10k_ce_shadow_src_ring_write_index_set(ar, ce_state, + write_index); + else + ath10k_ce_src_ring_write_index_set(ar, ctrl_addr, + write_index); + } src_ring->write_index = write_index; exit: @@ -1404,12 +1404,12 @@ static int ath10k_ce_alloc_shadow_base(struct ath10k *ar, u32 nentries) { src_ring->shadow_base_unaligned = kcalloc(nentries, - sizeof(struct ce_desc), + sizeof(struct ce_desc_64), GFP_KERNEL); if (!src_ring->shadow_base_unaligned) return -ENOMEM; - src_ring->shadow_base = (struct ce_desc *) + src_ring->shadow_base = (struct ce_desc_64 *) PTR_ALIGN(src_ring->shadow_base_unaligned, CE_DESC_RING_ALIGN); return 0; @@ -1461,7 +1461,7 @@ ath10k_ce_alloc_src_ring(struct ath10k *ar, unsigned int ce_id, ret = ath10k_ce_alloc_shadow_base(ar, src_ring, nentries); if (ret) { dma_free_coherent(ar->dev, - (nentries * sizeof(struct ce_desc) + + (nentries * sizeof(struct ce_desc_64) + CE_DESC_RING_ALIGN), src_ring->base_addr_owner_space_unaligned, base_addr); diff --git a/drivers/net/wireless/ath/ath10k/ce.h b/drivers/net/wireless/ath/ath10k/ce.h index ead9987..463e2fc 100644 --- a/drivers/net/wireless/ath/ath10k/ce.h +++ b/drivers/net/wireless/ath/ath10k/ce.h @@ -118,7 +118,7 @@ struct ath10k_ce_ring { u32 base_addr_ce_space; char *shadow_base_unaligned; - struct ce_desc *shadow_base; + struct ce_desc_64 *shadow_base; /* keep last */ void *per_transfer_context[0];
WCN3990 supports shadow registers write operation support for copy engine for regular operation in powersave mode. Since WCN3990 is a 64-bit target, the shadow register implementation needs to be done in the copy engine handlers for 64-bit target. Currently the shadow register implementation is present in the 32-bit target handlers of copy engine. Fix the shadow register copy engine write operation implementation for 64-bit target(WCN3990). Tested HW: WCN3990 Tested FW: WLAN.HL.2.0-01188-QCAHLSWMTPLZ-1 Fixes: b7ba83f7c414 ("ath10k: add support for shadow register for WNC3990") Signed-off-by: Rakesh Pillai <pillair@codeaurora.org> --- drivers/net/wireless/ath/ath10k/ce.c | 26 +++++++++++++------------- drivers/net/wireless/ath/ath10k/ce.h | 2 +- 2 files changed, 14 insertions(+), 14 deletions(-)