| Message ID | 20190419001014.23579-3-eric@anholt.net (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/4] drm/v3d: Fix debugfs reads of MMU regs. | expand |
Hi, On Thu, 2019-04-18 at 17:10 -0700, Eric Anholt wrote: > Looking at a hang recently, I noticed these registers that might tell > me if something obvious was wrong. They didn't help in this case, but > keep it around for the future. Although I don't have docs to check, looks sane: Reviewed-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Cheers, Paul > Signed-off-by: Eric Anholt <eric@anholt.net> > --- > drivers/gpu/drm/v3d/v3d_debugfs.c | 5 ++++ > drivers/gpu/drm/v3d/v3d_gem.c | 4 +++- > drivers/gpu/drm/v3d/v3d_regs.h | 38 +++++++++++++++++++++++++++++++ > 3 files changed, 46 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/v3d/v3d_debugfs.c b/drivers/gpu/drm/v3d/v3d_debugfs.c > index ab652a034959..78a78938e81f 100644 > --- a/drivers/gpu/drm/v3d/v3d_debugfs.c > +++ b/drivers/gpu/drm/v3d/v3d_debugfs.c > @@ -58,6 +58,11 @@ static const struct v3d_reg_def v3d_core_reg_defs[] = { > REGDEF(V3D_GMP_STATUS), > REGDEF(V3D_GMP_CFG), > REGDEF(V3D_GMP_VIO_ADDR), > + > + REGDEF(V3D_ERR_FDBGO), > + REGDEF(V3D_ERR_FDBGB), > + REGDEF(V3D_ERR_FDBGS), > + REGDEF(V3D_ERR_STAT), > }; > > static const struct v3d_reg_def v3d_csd_reg_defs[] = { > diff --git a/drivers/gpu/drm/v3d/v3d_gem.c b/drivers/gpu/drm/v3d/v3d_gem.c > index f736e021467a..27e0f87075d9 100644 > --- a/drivers/gpu/drm/v3d/v3d_gem.c > +++ b/drivers/gpu/drm/v3d/v3d_gem.c > @@ -109,7 +109,9 @@ v3d_reset(struct v3d_dev *v3d) > { > struct drm_device *dev = &v3d->drm; > > - DRM_ERROR("Resetting GPU.\n"); > + DRM_DEV_ERROR(dev->dev, "Resetting GPU for hang.\n"); > + DRM_DEV_ERROR(dev->dev, "V3D_ERR_STAT: 0x%08x\n", > + V3D_CORE_READ(0, V3D_ERR_STAT)); > trace_v3d_reset_begin(dev); > > /* XXX: only needed for safe powerdown, not reset. */ > diff --git a/drivers/gpu/drm/v3d/v3d_regs.h b/drivers/gpu/drm/v3d/v3d_regs.h > index 54c8c4320da0..eda1e289976f 100644 > --- a/drivers/gpu/drm/v3d/v3d_regs.h > +++ b/drivers/gpu/drm/v3d/v3d_regs.h > @@ -455,4 +455,42 @@ > # define V3D_CSD_CURRENT_ID0_WG_Y_MASK V3D_MASK(15, 0) > # define V3D_CSD_CURRENT_ID0_WG_Y_SHIFT 0 > > +#define V3D_ERR_FDBGO 0x00f04 > +#define V3D_ERR_FDBGB 0x00f08 > +#define V3D_ERR_FDBGR 0x00f0c > + > +#define V3D_ERR_FDBGS 0x00f10 > +# define V3D_ERR_FDBGS_INTERPZ_IP_STALL BIT(17) > +# define V3D_ERR_FDBGS_DEPTHO_FIFO_IP_STALL BIT(16) > +# define V3D_ERR_FDBGS_XYNRM_IP_STALL BIT(14) > +# define V3D_ERR_FDBGS_EZREQ_FIFO_OP_VALID BIT(13) > +# define V3D_ERR_FDBGS_QXYF_FIFO_OP_VALID BIT(12) > +# define V3D_ERR_FDBGS_QXYF_FIFO_OP_LAST BIT(11) > +# define V3D_ERR_FDBGS_EZTEST_ANYQVALID BIT(7) > +# define V3D_ERR_FDBGS_EZTEST_PASS BIT(6) > +# define V3D_ERR_FDBGS_EZTEST_QREADY BIT(5) > +# define V3D_ERR_FDBGS_EZTEST_VLF_OKNOVALID BIT(4) > +# define V3D_ERR_FDBGS_EZTEST_QSTALL BIT(3) > +# define V3D_ERR_FDBGS_EZTEST_IP_VLFSTALL BIT(2) > +# define V3D_ERR_FDBGS_EZTEST_IP_PRSTALL BIT(1) > +# define V3D_ERR_FDBGS_EZTEST_IP_QSTALL BIT(0) > + > +#define V3D_ERR_STAT 0x00f20 > +# define V3D_ERR_L2CARE BIT(15) > +# define V3D_ERR_VCMBE BIT(14) > +# define V3D_ERR_VCMRE BIT(13) > +# define V3D_ERR_VCDI BIT(12) > +# define V3D_ERR_VCDE BIT(11) > +# define V3D_ERR_VDWE BIT(10) > +# define V3D_ERR_VPMEAS BIT(9) > +# define V3D_ERR_VPMEFNA BIT(8) > +# define V3D_ERR_VPMEWNA BIT(7) > +# define V3D_ERR_VPMERNA BIT(6) > +# define V3D_ERR_VPMERR BIT(5) > +# define V3D_ERR_VPMEWR BIT(4) > +# define V3D_ERR_VPAERRGL BIT(3) > +# define V3D_ERR_VPAEBRGL BIT(2) > +# define V3D_ERR_VPAERGS BIT(1) > +# define V3D_ERR_VPAEABB BIT(0) > + > #endif /* V3D_REGS_H */
diff --git a/drivers/gpu/drm/v3d/v3d_debugfs.c b/drivers/gpu/drm/v3d/v3d_debugfs.c index ab652a034959..78a78938e81f 100644 --- a/drivers/gpu/drm/v3d/v3d_debugfs.c +++ b/drivers/gpu/drm/v3d/v3d_debugfs.c @@ -58,6 +58,11 @@ static const struct v3d_reg_def v3d_core_reg_defs[] = { REGDEF(V3D_GMP_STATUS), REGDEF(V3D_GMP_CFG), REGDEF(V3D_GMP_VIO_ADDR), + + REGDEF(V3D_ERR_FDBGO), + REGDEF(V3D_ERR_FDBGB), + REGDEF(V3D_ERR_FDBGS), + REGDEF(V3D_ERR_STAT), }; static const struct v3d_reg_def v3d_csd_reg_defs[] = { diff --git a/drivers/gpu/drm/v3d/v3d_gem.c b/drivers/gpu/drm/v3d/v3d_gem.c index f736e021467a..27e0f87075d9 100644 --- a/drivers/gpu/drm/v3d/v3d_gem.c +++ b/drivers/gpu/drm/v3d/v3d_gem.c @@ -109,7 +109,9 @@ v3d_reset(struct v3d_dev *v3d) { struct drm_device *dev = &v3d->drm; - DRM_ERROR("Resetting GPU.\n"); + DRM_DEV_ERROR(dev->dev, "Resetting GPU for hang.\n"); + DRM_DEV_ERROR(dev->dev, "V3D_ERR_STAT: 0x%08x\n", + V3D_CORE_READ(0, V3D_ERR_STAT)); trace_v3d_reset_begin(dev); /* XXX: only needed for safe powerdown, not reset. */ diff --git a/drivers/gpu/drm/v3d/v3d_regs.h b/drivers/gpu/drm/v3d/v3d_regs.h index 54c8c4320da0..eda1e289976f 100644 --- a/drivers/gpu/drm/v3d/v3d_regs.h +++ b/drivers/gpu/drm/v3d/v3d_regs.h @@ -455,4 +455,42 @@ # define V3D_CSD_CURRENT_ID0_WG_Y_MASK V3D_MASK(15, 0) # define V3D_CSD_CURRENT_ID0_WG_Y_SHIFT 0 +#define V3D_ERR_FDBGO 0x00f04 +#define V3D_ERR_FDBGB 0x00f08 +#define V3D_ERR_FDBGR 0x00f0c + +#define V3D_ERR_FDBGS 0x00f10 +# define V3D_ERR_FDBGS_INTERPZ_IP_STALL BIT(17) +# define V3D_ERR_FDBGS_DEPTHO_FIFO_IP_STALL BIT(16) +# define V3D_ERR_FDBGS_XYNRM_IP_STALL BIT(14) +# define V3D_ERR_FDBGS_EZREQ_FIFO_OP_VALID BIT(13) +# define V3D_ERR_FDBGS_QXYF_FIFO_OP_VALID BIT(12) +# define V3D_ERR_FDBGS_QXYF_FIFO_OP_LAST BIT(11) +# define V3D_ERR_FDBGS_EZTEST_ANYQVALID BIT(7) +# define V3D_ERR_FDBGS_EZTEST_PASS BIT(6) +# define V3D_ERR_FDBGS_EZTEST_QREADY BIT(5) +# define V3D_ERR_FDBGS_EZTEST_VLF_OKNOVALID BIT(4) +# define V3D_ERR_FDBGS_EZTEST_QSTALL BIT(3) +# define V3D_ERR_FDBGS_EZTEST_IP_VLFSTALL BIT(2) +# define V3D_ERR_FDBGS_EZTEST_IP_PRSTALL BIT(1) +# define V3D_ERR_FDBGS_EZTEST_IP_QSTALL BIT(0) + +#define V3D_ERR_STAT 0x00f20 +# define V3D_ERR_L2CARE BIT(15) +# define V3D_ERR_VCMBE BIT(14) +# define V3D_ERR_VCMRE BIT(13) +# define V3D_ERR_VCDI BIT(12) +# define V3D_ERR_VCDE BIT(11) +# define V3D_ERR_VDWE BIT(10) +# define V3D_ERR_VPMEAS BIT(9) +# define V3D_ERR_VPMEFNA BIT(8) +# define V3D_ERR_VPMEWNA BIT(7) +# define V3D_ERR_VPMERNA BIT(6) +# define V3D_ERR_VPMERR BIT(5) +# define V3D_ERR_VPMEWR BIT(4) +# define V3D_ERR_VPAERRGL BIT(3) +# define V3D_ERR_VPAEBRGL BIT(2) +# define V3D_ERR_VPAERGS BIT(1) +# define V3D_ERR_VPAEABB BIT(0) + #endif /* V3D_REGS_H */
Looking at a hang recently, I noticed these registers that might tell me if something obvious was wrong. They didn't help in this case, but keep it around for the future. Signed-off-by: Eric Anholt <eric@anholt.net> --- drivers/gpu/drm/v3d/v3d_debugfs.c | 5 ++++ drivers/gpu/drm/v3d/v3d_gem.c | 4 +++- drivers/gpu/drm/v3d/v3d_regs.h | 38 +++++++++++++++++++++++++++++++ 3 files changed, 46 insertions(+), 1 deletion(-)