| Message ID | 20190715182110.21336-9-jagan@amarulasolutions.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | ram: rk3399: Code cleanup | expand |
On 2019/7/16 上午2:21, Jagan Teki wrote: > Rename ca_tsel_wr_select_p to tsel_wr_select_ca_p based > on the bsp code. > > No functionality change. > > Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> > Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com> Thanks, - Kever > --- > drivers/ram/rockchip/sdram_rk3399.c | 10 +++++----- > 1 file changed, 5 insertions(+), 5 deletions(-) > > diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c > index bdb46a0128..8a983f9bb1 100644 > --- a/drivers/ram/rockchip/sdram_rk3399.c > +++ b/drivers/ram/rockchip/sdram_rk3399.c > @@ -160,14 +160,14 @@ static void set_ds_odt(const struct chan_info *chan, > > u32 tsel_idle_en, tsel_wr_en, tsel_rd_en; > u32 tsel_idle_select_p, tsel_wr_select_dq_p, tsel_rd_select_p; > - u32 ca_tsel_wr_select_p, tsel_wr_select_ca_n; > + u32 tsel_wr_select_ca_p, tsel_wr_select_ca_n; > u32 tsel_idle_select_n, tsel_wr_select_dq_n, tsel_rd_select_n; > u32 reg_value; > > if (params->base.dramtype == LPDDR4) { > tsel_rd_select_p = PHY_DRV_ODT_HI_Z; > tsel_wr_select_dq_p = PHY_DRV_ODT_40; > - ca_tsel_wr_select_p = PHY_DRV_ODT_40; > + tsel_wr_select_ca_p = PHY_DRV_ODT_40; > tsel_idle_select_p = PHY_DRV_ODT_HI_Z; > > tsel_rd_select_n = PHY_DRV_ODT_240; > @@ -177,7 +177,7 @@ static void set_ds_odt(const struct chan_info *chan, > } else if (params->base.dramtype == LPDDR3) { > tsel_rd_select_p = PHY_DRV_ODT_240; > tsel_wr_select_dq_p = PHY_DRV_ODT_34_3; > - ca_tsel_wr_select_p = PHY_DRV_ODT_48; > + tsel_wr_select_ca_p = PHY_DRV_ODT_48; > tsel_idle_select_p = PHY_DRV_ODT_240; > > tsel_rd_select_n = PHY_DRV_ODT_HI_Z; > @@ -187,7 +187,7 @@ static void set_ds_odt(const struct chan_info *chan, > } else { > tsel_rd_select_p = PHY_DRV_ODT_240; > tsel_wr_select_dq_p = PHY_DRV_ODT_34_3; > - ca_tsel_wr_select_p = PHY_DRV_ODT_34_3; > + tsel_wr_select_ca_p = PHY_DRV_ODT_34_3; > tsel_idle_select_p = PHY_DRV_ODT_240; > > tsel_rd_select_n = PHY_DRV_ODT_240; > @@ -228,7 +228,7 @@ static void set_ds_odt(const struct chan_info *chan, > clrsetbits_le32(&denali_phy[391], 0xffffff, reg_value); > > /* phy_adr_tsel_select_ 8bits DENALI_PHY_544/672/800 offset_0 */ > - reg_value = tsel_wr_select_ca_n | (ca_tsel_wr_select_p << 0x4); > + reg_value = tsel_wr_select_ca_n | (tsel_wr_select_ca_p << 0x4); > clrsetbits_le32(&denali_phy[544], 0xff, reg_value); > clrsetbits_le32(&denali_phy[672], 0xff, reg_value); > clrsetbits_le32(&denali_phy[800], 0xff, reg_value);
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index bdb46a0128..8a983f9bb1 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -160,14 +160,14 @@ static void set_ds_odt(const struct chan_info *chan, u32 tsel_idle_en, tsel_wr_en, tsel_rd_en; u32 tsel_idle_select_p, tsel_wr_select_dq_p, tsel_rd_select_p; - u32 ca_tsel_wr_select_p, tsel_wr_select_ca_n; + u32 tsel_wr_select_ca_p, tsel_wr_select_ca_n; u32 tsel_idle_select_n, tsel_wr_select_dq_n, tsel_rd_select_n; u32 reg_value; if (params->base.dramtype == LPDDR4) { tsel_rd_select_p = PHY_DRV_ODT_HI_Z; tsel_wr_select_dq_p = PHY_DRV_ODT_40; - ca_tsel_wr_select_p = PHY_DRV_ODT_40; + tsel_wr_select_ca_p = PHY_DRV_ODT_40; tsel_idle_select_p = PHY_DRV_ODT_HI_Z; tsel_rd_select_n = PHY_DRV_ODT_240; @@ -177,7 +177,7 @@ static void set_ds_odt(const struct chan_info *chan, } else if (params->base.dramtype == LPDDR3) { tsel_rd_select_p = PHY_DRV_ODT_240; tsel_wr_select_dq_p = PHY_DRV_ODT_34_3; - ca_tsel_wr_select_p = PHY_DRV_ODT_48; + tsel_wr_select_ca_p = PHY_DRV_ODT_48; tsel_idle_select_p = PHY_DRV_ODT_240; tsel_rd_select_n = PHY_DRV_ODT_HI_Z; @@ -187,7 +187,7 @@ static void set_ds_odt(const struct chan_info *chan, } else { tsel_rd_select_p = PHY_DRV_ODT_240; tsel_wr_select_dq_p = PHY_DRV_ODT_34_3; - ca_tsel_wr_select_p = PHY_DRV_ODT_34_3; + tsel_wr_select_ca_p = PHY_DRV_ODT_34_3; tsel_idle_select_p = PHY_DRV_ODT_240; tsel_rd_select_n = PHY_DRV_ODT_240; @@ -228,7 +228,7 @@ static void set_ds_odt(const struct chan_info *chan, clrsetbits_le32(&denali_phy[391], 0xffffff, reg_value); /* phy_adr_tsel_select_ 8bits DENALI_PHY_544/672/800 offset_0 */ - reg_value = tsel_wr_select_ca_n | (ca_tsel_wr_select_p << 0x4); + reg_value = tsel_wr_select_ca_n | (tsel_wr_select_ca_p << 0x4); clrsetbits_le32(&denali_phy[544], 0xff, reg_value); clrsetbits_le32(&denali_phy[672], 0xff, reg_value); clrsetbits_le32(&denali_phy[800], 0xff, reg_value);