[v3,09/15] ram: rk3399: Order tsel variables
diff mbox series

Message ID 20190715182110.21336-10-jagan@amarulasolutions.com
State New
Headers show
Series
  • ram: rk3399: Code cleanup
Related show

Commit Message

Jagan Teki July 15, 2019, 6:21 p.m. UTC
Order tsel* variable declarations and assignment in proper
and meaningful way.

No functionality change.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
---
 drivers/ram/rockchip/sdram_rk3399.c | 37 +++++++++++++++++------------
 1 file changed, 22 insertions(+), 15 deletions(-)

Comments

Kever Yang July 16, 2019, 7:32 a.m. UTC | #1
On 2019/7/16 上午2:21, Jagan Teki wrote:
> Order tsel* variable declarations and assignment in proper
> and meaningful way.
>
> No functionality change.
>
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> Signed-off-by: YouMin Chen <cym@rock-chips.com>

Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>

Thanks,
  - Kever
> ---
>   drivers/ram/rockchip/sdram_rk3399.c | 37 +++++++++++++++++------------
>   1 file changed, 22 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
> index 8a983f9bb1..043b27737d 100644
> --- a/drivers/ram/rockchip/sdram_rk3399.c
> +++ b/drivers/ram/rockchip/sdram_rk3399.c
> @@ -159,41 +159,48 @@ static void set_ds_odt(const struct chan_info *chan,
>   	u32 *denali_phy = chan->publ->denali_phy;
>   
>   	u32 tsel_idle_en, tsel_wr_en, tsel_rd_en;
> -	u32 tsel_idle_select_p, tsel_wr_select_dq_p, tsel_rd_select_p;
> -	u32 tsel_wr_select_ca_p, tsel_wr_select_ca_n;
> -	u32 tsel_idle_select_n, tsel_wr_select_dq_n, tsel_rd_select_n;
> +	u32 tsel_idle_select_p, tsel_rd_select_p;
> +	u32 tsel_idle_select_n, tsel_rd_select_n;
> +	u32 tsel_wr_select_dq_p, tsel_wr_select_ca_p;
> +	u32 tsel_wr_select_dq_n, tsel_wr_select_ca_n;
>   	u32 reg_value;
>   
>   	if (params->base.dramtype == LPDDR4) {
>   		tsel_rd_select_p = PHY_DRV_ODT_HI_Z;
> -		tsel_wr_select_dq_p = PHY_DRV_ODT_40;
> -		tsel_wr_select_ca_p = PHY_DRV_ODT_40;
> +		tsel_rd_select_n = PHY_DRV_ODT_240;
> +
>   		tsel_idle_select_p = PHY_DRV_ODT_HI_Z;
> +		tsel_idle_select_n = PHY_DRV_ODT_240;
>   
> -		tsel_rd_select_n = PHY_DRV_ODT_240;
> +		tsel_wr_select_dq_p = PHY_DRV_ODT_40;
>   		tsel_wr_select_dq_n = PHY_DRV_ODT_40;
> +
> +		tsel_wr_select_ca_p = PHY_DRV_ODT_40;
>   		tsel_wr_select_ca_n = PHY_DRV_ODT_40;
> -		tsel_idle_select_n = PHY_DRV_ODT_240;
>   	} else if (params->base.dramtype == LPDDR3) {
>   		tsel_rd_select_p = PHY_DRV_ODT_240;
> -		tsel_wr_select_dq_p = PHY_DRV_ODT_34_3;
> -		tsel_wr_select_ca_p = PHY_DRV_ODT_48;
> +		tsel_rd_select_n = PHY_DRV_ODT_HI_Z;
> +
>   		tsel_idle_select_p = PHY_DRV_ODT_240;
> +		tsel_idle_select_n = PHY_DRV_ODT_HI_Z;
>   
> -		tsel_rd_select_n = PHY_DRV_ODT_HI_Z;
> +		tsel_wr_select_dq_p = PHY_DRV_ODT_34_3;
>   		tsel_wr_select_dq_n = PHY_DRV_ODT_34_3;
> +
> +		tsel_wr_select_ca_p = PHY_DRV_ODT_48;
>   		tsel_wr_select_ca_n = PHY_DRV_ODT_48;
> -		tsel_idle_select_n = PHY_DRV_ODT_HI_Z;
>   	} else {
>   		tsel_rd_select_p = PHY_DRV_ODT_240;
> -		tsel_wr_select_dq_p = PHY_DRV_ODT_34_3;
> -		tsel_wr_select_ca_p = PHY_DRV_ODT_34_3;
> +		tsel_rd_select_n = PHY_DRV_ODT_240;
> +
>   		tsel_idle_select_p = PHY_DRV_ODT_240;
> +		tsel_idle_select_n = PHY_DRV_ODT_240;
>   
> -		tsel_rd_select_n = PHY_DRV_ODT_240;
> +		tsel_wr_select_dq_p = PHY_DRV_ODT_34_3;
>   		tsel_wr_select_dq_n = PHY_DRV_ODT_34_3;
> +
> +		tsel_wr_select_ca_p = PHY_DRV_ODT_34_3;
>   		tsel_wr_select_ca_n = PHY_DRV_ODT_34_3;
> -		tsel_idle_select_n = PHY_DRV_ODT_240;
>   	}
>   
>   	if (params->base.odt == 1)

Patch
diff mbox series

diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 8a983f9bb1..043b27737d 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -159,41 +159,48 @@  static void set_ds_odt(const struct chan_info *chan,
 	u32 *denali_phy = chan->publ->denali_phy;
 
 	u32 tsel_idle_en, tsel_wr_en, tsel_rd_en;
-	u32 tsel_idle_select_p, tsel_wr_select_dq_p, tsel_rd_select_p;
-	u32 tsel_wr_select_ca_p, tsel_wr_select_ca_n;
-	u32 tsel_idle_select_n, tsel_wr_select_dq_n, tsel_rd_select_n;
+	u32 tsel_idle_select_p, tsel_rd_select_p;
+	u32 tsel_idle_select_n, tsel_rd_select_n;
+	u32 tsel_wr_select_dq_p, tsel_wr_select_ca_p;
+	u32 tsel_wr_select_dq_n, tsel_wr_select_ca_n;
 	u32 reg_value;
 
 	if (params->base.dramtype == LPDDR4) {
 		tsel_rd_select_p = PHY_DRV_ODT_HI_Z;
-		tsel_wr_select_dq_p = PHY_DRV_ODT_40;
-		tsel_wr_select_ca_p = PHY_DRV_ODT_40;
+		tsel_rd_select_n = PHY_DRV_ODT_240;
+
 		tsel_idle_select_p = PHY_DRV_ODT_HI_Z;
+		tsel_idle_select_n = PHY_DRV_ODT_240;
 
-		tsel_rd_select_n = PHY_DRV_ODT_240;
+		tsel_wr_select_dq_p = PHY_DRV_ODT_40;
 		tsel_wr_select_dq_n = PHY_DRV_ODT_40;
+
+		tsel_wr_select_ca_p = PHY_DRV_ODT_40;
 		tsel_wr_select_ca_n = PHY_DRV_ODT_40;
-		tsel_idle_select_n = PHY_DRV_ODT_240;
 	} else if (params->base.dramtype == LPDDR3) {
 		tsel_rd_select_p = PHY_DRV_ODT_240;
-		tsel_wr_select_dq_p = PHY_DRV_ODT_34_3;
-		tsel_wr_select_ca_p = PHY_DRV_ODT_48;
+		tsel_rd_select_n = PHY_DRV_ODT_HI_Z;
+
 		tsel_idle_select_p = PHY_DRV_ODT_240;
+		tsel_idle_select_n = PHY_DRV_ODT_HI_Z;
 
-		tsel_rd_select_n = PHY_DRV_ODT_HI_Z;
+		tsel_wr_select_dq_p = PHY_DRV_ODT_34_3;
 		tsel_wr_select_dq_n = PHY_DRV_ODT_34_3;
+
+		tsel_wr_select_ca_p = PHY_DRV_ODT_48;
 		tsel_wr_select_ca_n = PHY_DRV_ODT_48;
-		tsel_idle_select_n = PHY_DRV_ODT_HI_Z;
 	} else {
 		tsel_rd_select_p = PHY_DRV_ODT_240;
-		tsel_wr_select_dq_p = PHY_DRV_ODT_34_3;
-		tsel_wr_select_ca_p = PHY_DRV_ODT_34_3;
+		tsel_rd_select_n = PHY_DRV_ODT_240;
+
 		tsel_idle_select_p = PHY_DRV_ODT_240;
+		tsel_idle_select_n = PHY_DRV_ODT_240;
 
-		tsel_rd_select_n = PHY_DRV_ODT_240;
+		tsel_wr_select_dq_p = PHY_DRV_ODT_34_3;
 		tsel_wr_select_dq_n = PHY_DRV_ODT_34_3;
+
+		tsel_wr_select_ca_p = PHY_DRV_ODT_34_3;
 		tsel_wr_select_ca_n = PHY_DRV_ODT_34_3;
-		tsel_idle_select_n = PHY_DRV_ODT_240;
 	}
 
 	if (params->base.odt == 1)