diff mbox series

ath10k: use ath10k_pci_soc_ functions for all warm_reset instances

Message ID 1564305118-3059-1-git-send-email-pozega.tomislav@gmail.com (mailing list archive)
State Accepted
Commit 9c44bf4c12550f1c3c1be0671e559477e70ab350
Delegated to: Kalle Valo
Headers show
Series ath10k: use ath10k_pci_soc_ functions for all warm_reset instances | expand

Commit Message

Tom Psyborg July 28, 2019, 9:11 a.m. UTC
Use ath10k_pci_soc_read32 / ath10k_pci_soc_write32 functions for
the rest of warm_reset functions. Until now these have been used
only for ath10k_pci_warm_reset_si0, but since they already exist
it makes sense to simplify code a bit.
Runtime tested with QCA9862.

Signed-off-by: Tomislav Požega <pozega.tomislav@gmail.com>
---
 drivers/net/wireless/ath/ath10k/pci.c |   26 +++++++++++---------------
 1 files changed, 11 insertions(+), 15 deletions(-)

Comments

Kalle Valo Sept. 17, 2019, 2:10 p.m. UTC | #1
Tomislav Požega wrote:

> Use ath10k_pci_soc_read32 / ath10k_pci_soc_write32 functions for
> the rest of warm_reset functions. Until now these have been used
> only for ath10k_pci_warm_reset_si0, but since they already exist
> it makes sense to simplify code a bit.
> Runtime tested with QCA9862.
> 
> Signed-off-by: Tomislav Požega <pozega.tomislav@gmail.com>
> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>

Patch applied to ath-next branch of ath.git, thanks.

9c44bf4c1255 ath10k: use ath10k_pci_soc_ functions for all warm_reset instances
Tom Psyborg Sept. 17, 2019, 4:54 p.m. UTC | #2
On 17/09/2019, Kalle Valo <kvalo@codeaurora.org> wrote:
> Tomislav Požega wrote:
>
>> Use ath10k_pci_soc_read32 / ath10k_pci_soc_write32 functions for
>> the rest of warm_reset functions. Until now these have been used
>> only for ath10k_pci_warm_reset_si0, but since they already exist
>> it makes sense to simplify code a bit.
>> Runtime tested with QCA9862.
>>
>> Signed-off-by: Tomislav Požega <pozega.tomislav@gmail.com>
>> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
>
is this a typo or should've I add your SoB line to that commit? btw
what about this patch it's been sent out quite a several months ago?
https://patchwork.kernel.org/patch/10860301/
Kalle Valo Sept. 17, 2019, 5:30 p.m. UTC | #3
Tom Psyborg <pozega.tomislav@gmail.com> writes:

> On 17/09/2019, Kalle Valo <kvalo@codeaurora.org> wrote:
>> Tomislav Požega wrote:
>>
>>> Use ath10k_pci_soc_read32 / ath10k_pci_soc_write32 functions for
>>> the rest of warm_reset functions. Until now these have been used
>>> only for ath10k_pci_warm_reset_si0, but since they already exist
>>> it makes sense to simplify code a bit.
>>> Runtime tested with QCA9862.
>>>
>>> Signed-off-by: Tomislav Požega <pozega.tomislav@gmail.com>
>>> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
>
> is this a typo or should've I add your SoB line to that commit?

This is just because of my pwcli patchwork script and it's stgit mode.
It takes the commit log directly from the pending branch, where I need
to add my s-o-b as I publish the branch.

In general you should only add your own s-o-b line:

https://www.kernel.org/doc/html/latest/process/submitting-patches.html#sign-your-work-the-developer-s-certificate-of-origin

> btw what about this patch it's been sent out quite a several months
> ago? https://patchwork.kernel.org/patch/10860301/

I have not looked at that yet but it's in my queue.
diff mbox series

Patch

diff --git a/drivers/net/wireless/ath/ath10k/pci.c b/drivers/net/wireless/ath/ath10k/pci.c
index a0b4d26..bf16f17 100644
--- a/drivers/net/wireless/ath/ath10k/pci.c
+++ b/drivers/net/wireless/ath/ath10k/pci.c
@@ -2567,35 +2567,31 @@  static void ath10k_pci_warm_reset_cpu(struct ath10k *ar)
 
 	ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS, 0);
 
-	val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
-				SOC_RESET_CONTROL_ADDRESS);
-	ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS,
-			   val | SOC_RESET_CONTROL_CPU_WARM_RST_MASK);
+	val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
+	ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS,
+				val | SOC_RESET_CONTROL_CPU_WARM_RST_MASK);
 }
 
 static void ath10k_pci_warm_reset_ce(struct ath10k *ar)
 {
 	u32 val;
 
-	val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
-				SOC_RESET_CONTROL_ADDRESS);
+	val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
 
-	ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS,
-			   val | SOC_RESET_CONTROL_CE_RST_MASK);
+	ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS,
+				val | SOC_RESET_CONTROL_CE_RST_MASK);
 	msleep(10);
-	ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS,
-			   val & ~SOC_RESET_CONTROL_CE_RST_MASK);
+	ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS,
+				val & ~SOC_RESET_CONTROL_CE_RST_MASK);
 }
 
 static void ath10k_pci_warm_reset_clear_lf(struct ath10k *ar)
 {
 	u32 val;
 
-	val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
-				SOC_LF_TIMER_CONTROL0_ADDRESS);
-	ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS +
-			   SOC_LF_TIMER_CONTROL0_ADDRESS,
-			   val & ~SOC_LF_TIMER_CONTROL0_ENABLE_MASK);
+	val = ath10k_pci_soc_read32(ar, SOC_LF_TIMER_CONTROL0_ADDRESS);
+	ath10k_pci_soc_write32(ar, SOC_LF_TIMER_CONTROL0_ADDRESS,
+				val & ~SOC_LF_TIMER_CONTROL0_ENABLE_MASK);
 }
 
 static int ath10k_pci_warm_reset(struct ath10k *ar)