[RFC,2/3] drm/i915: introduce display_uncore
diff mbox series

Message ID 20190808014423.20377-3-daniele.ceraolospurio@intel.com
State New
Headers show
Series
  • Display uncore
Related show

Commit Message

Daniele Ceraolo Spurio Aug. 8, 2019, 1:44 a.m. UTC
A forcewake-less uncore to be used to decouple GT accesses from display
ones to avoid serializing them when there is no need.

New accessors that implicitly use the new uncore have also been added.
To avoid accessing the same register from 2 different uncores (which
could cause hard hangs), the new accessors expect registers to be
defined with the new _DE_MMIO macro.

Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 .../gpu/drm/i915/display/intel_display_reg.h  | 22 +++++++++++++
 drivers/gpu/drm/i915/i915_drv.c               | 17 ++++++++--
 drivers/gpu/drm/i915/i915_drv.h               | 31 +++++++++++++++++++
 drivers/gpu/drm/i915/intel_uncore.c           |  9 +++++-
 4 files changed, 76 insertions(+), 3 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/intel_display_reg.h

Patch
diff mbox series

diff --git a/drivers/gpu/drm/i915/display/intel_display_reg.h b/drivers/gpu/drm/i915/display/intel_display_reg.h
new file mode 100644
index 000000000000..ac0c6975271d
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_display_reg.h
@@ -0,0 +1,22 @@ 
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2019 Intel Corporation
+ */
+
+#ifndef _INTEL_DISPLAY_REG_H_
+#define _INTEL_DISPLAY_REG_H_
+
+#include "i915_reg.h"
+
+typedef struct {
+	const i915_reg_t reg;
+} intel_de_reg_t;
+
+#define _DE_MMIO(r) ((const intel_de_reg_t){ .reg = _MMIO(r) })
+
+static inline i915_reg_t intel_de_reg_to_mmio(intel_de_reg_t reg)
+{
+	return reg.reg;
+}
+
+#endif
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index fbbff4a133ba..af015ecf3dcc 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -746,6 +746,7 @@  static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
 
 	intel_uncore_mmio_debug_init_early(&dev_priv->mmio_debug);
 	intel_uncore_init_early(&dev_priv->uncore, dev_priv);
+	intel_uncore_init_early(&dev_priv->de_uncore, dev_priv);
 
 	spin_lock_init(&dev_priv->irq_lock);
 	spin_lock_init(&dev_priv->gpu_error.lock);
@@ -841,6 +842,10 @@  static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv)
 	if (ret < 0)
 		goto err_bridge;
 
+	ret = intel_uncore_init_mmio(&dev_priv->de_uncore);
+	if (ret < 0)
+		goto err_uncore;
+
 	/* Try to make sure MCHBAR is enabled before poking at it */
 	intel_setup_mchbar(dev_priv);
 
@@ -852,14 +857,16 @@  static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv)
 
 	ret = intel_engines_init_mmio(dev_priv);
 	if (ret)
-		goto err_uncore;
+		goto err_mchbar;
 
 	i915_gem_init_mmio(dev_priv);
 
 	return 0;
 
-err_uncore:
+err_mchbar:
 	intel_teardown_mchbar(dev_priv);
+	intel_uncore_fini_mmio(&dev_priv->de_uncore);
+err_uncore:
 	intel_uncore_fini_mmio(&dev_priv->uncore);
 err_bridge:
 	pci_dev_put(dev_priv->bridge_dev);
@@ -875,6 +882,7 @@  static void i915_driver_mmio_release(struct drm_i915_private *dev_priv)
 {
 	intel_engines_cleanup(dev_priv);
 	intel_teardown_mchbar(dev_priv);
+	intel_uncore_fini_mmio(&dev_priv->de_uncore);
 	intel_uncore_fini_mmio(&dev_priv->uncore);
 	pci_dev_put(dev_priv->bridge_dev);
 }
@@ -2010,6 +2018,7 @@  static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
 
 	i915_gem_suspend_late(dev_priv);
 
+	intel_uncore_suspend(&dev_priv->de_uncore);
 	intel_uncore_suspend(&dev_priv->uncore);
 
 	intel_power_domains_suspend(dev_priv,
@@ -2199,6 +2208,7 @@  static int i915_drm_resume_early(struct drm_device *dev)
 			  ret);
 
 	intel_uncore_resume_early(&dev_priv->uncore);
+	intel_uncore_resume_early(&dev_priv->de_uncore);
 
 	intel_gt_check_and_clear_faults(&dev_priv->gt);
 
@@ -2764,6 +2774,7 @@  static int intel_runtime_suspend(struct device *kdev)
 
 	intel_runtime_pm_disable_interrupts(dev_priv);
 
+	intel_uncore_suspend(&dev_priv->de_uncore);
 	intel_uncore_suspend(&dev_priv->uncore);
 
 	intel_display_power_suspend(dev_priv);
@@ -2774,6 +2785,7 @@  static int intel_runtime_suspend(struct device *kdev)
 	if (ret) {
 		DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
 		intel_uncore_runtime_resume(&dev_priv->uncore);
+		intel_uncore_runtime_resume(&dev_priv->de_uncore);
 
 		intel_runtime_pm_enable_interrupts(dev_priv);
 
@@ -2851,6 +2863,7 @@  static int intel_runtime_resume(struct device *kdev)
 		ret = vlv_resume_prepare(dev_priv, true);
 
 	intel_uncore_runtime_resume(&dev_priv->uncore);
+	intel_uncore_runtime_resume(&dev_priv->de_uncore);
 
 	intel_runtime_pm_enable_interrupts(dev_priv);
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 13c27a75dca8..015b490c14d6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -66,6 +66,7 @@ 
 #include "display/intel_bios.h"
 #include "display/intel_display.h"
 #include "display/intel_display_power.h"
+#include "display/intel_display_reg.h"
 #include "display/intel_dpll_mgr.h"
 #include "display/intel_frontbuffer.h"
 #include "display/intel_opregion.h"
@@ -1346,6 +1347,7 @@  struct drm_i915_private {
 	resource_size_t stolen_usable_size;	/* Total size minus reserved ranges */
 
 	struct intel_uncore uncore;
+	struct intel_uncore de_uncore;
 	struct intel_uncore_mmio_debug mmio_debug;
 
 	struct i915_virtual_gpu vgpu;
@@ -2687,6 +2689,35 @@  int i915_reg_read_ioctl(struct drm_device *dev, void *data,
 #define I915_READ_FW(reg__) __I915_REG_OP(read_fw, dev_priv, (reg__))
 #define I915_WRITE_FW(reg__, val__) __I915_REG_OP(write_fw, dev_priv, (reg__), (val__))
 
+/*
+ * The following are mmio-accessors that use an independent lock and skip all
+ * the forcewake logic, to be used to access display registers, which are
+ * outside the GT forcewake wells.
+ */
+static inline u32
+intel_de_read(struct drm_i915_private *i915, intel_de_reg_t reg)
+{
+	return intel_uncore_read(&i915->de_uncore, intel_de_reg_to_mmio(reg));
+}
+
+static inline void
+intel_de_posting_read(struct drm_i915_private *i915, intel_de_reg_t reg)
+{
+	intel_uncore_posting_read(&i915->de_uncore, intel_de_reg_to_mmio(reg));
+}
+
+static inline void
+intel_de_write(struct drm_i915_private *i915, intel_de_reg_t reg, u32 val)
+{
+	intel_uncore_write(&i915->de_uncore, intel_de_reg_to_mmio(reg), val);
+}
+
+static inline void
+intel_de_rmw(struct drm_i915_private *i915, intel_de_reg_t reg, u32 clear, u32 set)
+{
+	intel_uncore_rmw(&i915->de_uncore, intel_de_reg_to_mmio(reg), clear, set);
+}
+
 void i915_memcpy_init_early(struct drm_i915_private *dev_priv);
 bool i915_memcpy_from_wc(void *dst, const void *src, unsigned long len);
 
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 9e583f13a9e4..fba5e2a63888 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1702,6 +1702,12 @@  static int uncore_forcewake_init(struct intel_uncore *uncore)
 	return 0;
 }
 
+static bool
+intel_uncore_is_display(const struct intel_uncore *uncore)
+{
+	return uncore == &uncore->i915->de_uncore;
+}
+
 int intel_uncore_init_mmio(struct intel_uncore *uncore)
 {
 	struct drm_i915_private *i915 = uncore->i915;
@@ -1711,7 +1717,8 @@  int intel_uncore_init_mmio(struct intel_uncore *uncore)
 	if (ret)
 		return ret;
 
-	if (INTEL_GEN(i915) > 5 && !intel_vgpu_active(i915))
+	if (INTEL_GEN(i915) > 5 && !intel_vgpu_active(i915) &&
+	    !intel_uncore_is_display(uncore))
 		uncore->flags |= UNCORE_HAS_FORCEWAKE;
 
 	if (!intel_uncore_has_forcewake(uncore)) {