| Message ID | 20190823082055.5992-5-lucas.demarchi@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Tiger Lake batch 3 | expand |
On Fri, Aug 23, 2019 at 01:20:36AM -0700, Lucas De Marchi wrote: > From: José Roberto de Souza <jose.souza@intel.com> > > From BDW+ the PSR registers moved from DDIA to transcoder, so any port > with a eDP panel connected can have PSR, so lets remove this > limitation. > > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> > Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com> > --- > drivers/gpu/drm/i915/display/intel_psr.c | 6 ++---- > 1 file changed, 2 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c > index 81e3619cd905..0172b82858d9 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr.c > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > @@ -588,11 +588,9 @@ void intel_psr_compute_config(struct intel_dp *intel_dp, > > /* > * HSW spec explicitly says PSR is tied to port A. > - * BDW+ platforms have a instance of PSR registers per transcoder but > - * for now it only supports one instance of PSR, so lets keep it > - * hardcoded to PORT_A > + * BDW+ platforms have a instance of PSR registers per transcoder. > */ > - if (dig_port->base.port != PORT_A) { > + if (IS_HASWELL(dev_priv) && dig_port->base.port != PORT_A) { Based on an earlier discussion with Art, before TGL PSR is not supposed to be used anywhere else than port A. Art could you confirm that? > DRM_DEBUG_KMS("PSR condition failed: Port not supported\n"); > return; > } > -- > 2.23.0 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> -----Original Message----- > From: Imre Deak <imre.deak@intel.com> > Sent: Monday, 26 August, 2019 6:42 AM > To: Souza, Jose <jose.souza@intel.com>; De Marchi, Lucas > <lucas.demarchi@intel.com>; Runyan, Arthur J <arthur.j.runyan@intel.com> > Cc: intel-gfx@lists.freedesktop.org; Pandiyan, Dhinakaran > <dhinakaran.pandiyan@intel.com> > Subject: Re: [Intel-gfx] [PATCH v3 04/23] drm/i915/bdw+: Enable PSR in any > eDP port > > On Fri, Aug 23, 2019 at 01:20:36AM -0700, Lucas De Marchi wrote: > > From: José Roberto de Souza <jose.souza@intel.com> > > > > From BDW+ the PSR registers moved from DDIA to transcoder, so any port > > with a eDP panel connected can have PSR, so lets remove this > > limitation. > > > > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com> > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> > > Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_psr.c | 6 ++---- > > 1 file changed, 2 insertions(+), 4 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c > b/drivers/gpu/drm/i915/display/intel_psr.c > > index 81e3619cd905..0172b82858d9 100644 > > --- a/drivers/gpu/drm/i915/display/intel_psr.c > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > > @@ -588,11 +588,9 @@ void intel_psr_compute_config(struct intel_dp > *intel_dp, > > > > /* > > * HSW spec explicitly says PSR is tied to port A. > > - * BDW+ platforms have a instance of PSR registers per transcoder but > > - * for now it only supports one instance of PSR, so lets keep it > > - * hardcoded to PORT_A > > + * BDW+ platforms have a instance of PSR registers per transcoder. > > */ > > - if (dig_port->base.port != PORT_A) { > > + if (IS_HASWELL(dev_priv) && dig_port->base.port != PORT_A) { > > Based on an earlier discussion with Art, before TGL PSR is not supposed > to be used anywhere else than port A. > > Art could you confirm that? Correct. PSR1 is limited to DDIA until Tigerlake. There are registers for PSR on the other transcoders/ports because of reuse, but hardware isn't fully hooked up or validated. PSR2 is still limited to DDIA on Tigerlake. > > > DRM_DEBUG_KMS("PSR condition failed: Port not > supported\n"); > > return; > > } > > -- > > 2.23.0 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Mon, Aug 26, 2019 at 10:43:36AM -0700, Runyan, Arthur J wrote: >> -----Original Message----- >> From: Imre Deak <imre.deak@intel.com> >> Sent: Monday, 26 August, 2019 6:42 AM >> To: Souza, Jose <jose.souza@intel.com>; De Marchi, Lucas >> <lucas.demarchi@intel.com>; Runyan, Arthur J <arthur.j.runyan@intel.com> >> Cc: intel-gfx@lists.freedesktop.org; Pandiyan, Dhinakaran >> <dhinakaran.pandiyan@intel.com> >> Subject: Re: [Intel-gfx] [PATCH v3 04/23] drm/i915/bdw+: Enable PSR in any >> eDP port >> >> On Fri, Aug 23, 2019 at 01:20:36AM -0700, Lucas De Marchi wrote: >> > From: José Roberto de Souza <jose.souza@intel.com> >> > >> > From BDW+ the PSR registers moved from DDIA to transcoder, so any port >> > with a eDP panel connected can have PSR, so lets remove this >> > limitation. >> > >> > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> >> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> >> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com> >> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> >> > Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com> >> > --- >> > drivers/gpu/drm/i915/display/intel_psr.c | 6 ++---- >> > 1 file changed, 2 insertions(+), 4 deletions(-) >> > >> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c >> b/drivers/gpu/drm/i915/display/intel_psr.c >> > index 81e3619cd905..0172b82858d9 100644 >> > --- a/drivers/gpu/drm/i915/display/intel_psr.c >> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c >> > @@ -588,11 +588,9 @@ void intel_psr_compute_config(struct intel_dp >> *intel_dp, >> > >> > /* >> > * HSW spec explicitly says PSR is tied to port A. >> > - * BDW+ platforms have a instance of PSR registers per transcoder but >> > - * for now it only supports one instance of PSR, so lets keep it >> > - * hardcoded to PORT_A >> > + * BDW+ platforms have a instance of PSR registers per transcoder. >> > */ >> > - if (dig_port->base.port != PORT_A) { >> > + if (IS_HASWELL(dev_priv) && dig_port->base.port != PORT_A) { >> >> Based on an earlier discussion with Art, before TGL PSR is not supposed >> to be used anywhere else than port A. >> >> Art could you confirm that? > >Correct. >PSR1 is limited to DDIA until Tigerlake. There are registers for PSR on the other >transcoders/ports because of reuse, but hardware isn't fully hooked up or validated. >PSR2 is still limited to DDIA on Tigerlake. thank you both for confirming. José, I think we need to drop this patch and rebase the rest so we don't do anything before Tiger Lake. I will work on it. Lucas De Marchi > >> >> > DRM_DEBUG_KMS("PSR condition failed: Port not >> supported\n"); >> > return; >> > } >> > -- >> > 2.23.0 >> > >> > _______________________________________________ >> > Intel-gfx mailing list >> > Intel-gfx@lists.freedesktop.org >> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Tue, 2019-08-27 at 09:36 -0700, Lucas De Marchi wrote: > On Mon, Aug 26, 2019 at 10:43:36AM -0700, Runyan, Arthur J wrote: > > > -----Original Message----- > > > From: Imre Deak <imre.deak@intel.com> > > > Sent: Monday, 26 August, 2019 6:42 AM > > > To: Souza, Jose <jose.souza@intel.com>; De Marchi, Lucas > > > <lucas.demarchi@intel.com>; Runyan, Arthur J < > > > arthur.j.runyan@intel.com> > > > Cc: intel-gfx@lists.freedesktop.org; Pandiyan, Dhinakaran > > > <dhinakaran.pandiyan@intel.com> > > > Subject: Re: [Intel-gfx] [PATCH v3 04/23] drm/i915/bdw+: Enable > > > PSR in any > > > eDP port > > > > > > On Fri, Aug 23, 2019 at 01:20:36AM -0700, Lucas De Marchi wrote: > > > > From: José Roberto de Souza <jose.souza@intel.com> > > > > > > > > From BDW+ the PSR registers moved from DDIA to transcoder, so > > > > any port > > > > with a eDP panel connected can have PSR, so lets remove this > > > > limitation. > > > > > > > > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> > > > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> > > > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com> > > > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> > > > > Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com> > > > > --- > > > > drivers/gpu/drm/i915/display/intel_psr.c | 6 ++---- > > > > 1 file changed, 2 insertions(+), 4 deletions(-) > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c > > > b/drivers/gpu/drm/i915/display/intel_psr.c > > > > index 81e3619cd905..0172b82858d9 100644 > > > > --- a/drivers/gpu/drm/i915/display/intel_psr.c > > > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > > > > @@ -588,11 +588,9 @@ void intel_psr_compute_config(struct > > > > intel_dp > > > *intel_dp, > > > > /* > > > > * HSW spec explicitly says PSR is tied to port A. > > > > - * BDW+ platforms have a instance of PSR registers per > > > > transcoder but > > > > - * for now it only supports one instance of PSR, so > > > > lets keep it > > > > - * hardcoded to PORT_A > > > > + * BDW+ platforms have a instance of PSR registers per > > > > transcoder. > > > > */ > > > > - if (dig_port->base.port != PORT_A) { > > > > + if (IS_HASWELL(dev_priv) && dig_port->base.port != > > > > PORT_A) { > > > > > > Based on an earlier discussion with Art, before TGL PSR is not > > > supposed > > > to be used anywhere else than port A. > > > > > > Art could you confirm that? > > > > Correct. > > PSR1 is limited to DDIA until Tigerlake. There are registers for > > PSR on the other > > transcoders/ports because of reuse, but hardware isn't fully hooked > > up or validated. > > PSR2 is still limited to DDIA on Tigerlake. > > thank you both for confirming. José, I think we need to drop this > patch > and rebase the rest so we don't do anything before Tiger Lake. I will > work on it. Thanks, maybe write a patch updating the comment above would be nice. Otherwise I can do it latter. > > Lucas De Marchi > > > > > DRM_DEBUG_KMS("PSR condition failed: Port not > > > supported\n"); > > > > return; > > > > } > > > > -- > > > > 2.23.0 > > > > > > > > _______________________________________________ > > > > Intel-gfx mailing list > > > > Intel-gfx@lists.freedesktop.org > > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 81e3619cd905..0172b82858d9 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -588,11 +588,9 @@ void intel_psr_compute_config(struct intel_dp *intel_dp, /* * HSW spec explicitly says PSR is tied to port A. - * BDW+ platforms have a instance of PSR registers per transcoder but - * for now it only supports one instance of PSR, so lets keep it - * hardcoded to PORT_A + * BDW+ platforms have a instance of PSR registers per transcoder. */ - if (dig_port->base.port != PORT_A) { + if (IS_HASWELL(dev_priv) && dig_port->base.port != PORT_A) { DRM_DEBUG_KMS("PSR condition failed: Port not supported\n"); return; }