| Message ID | 1571900044-22079-1-git-send-email-peng.fan@nxp.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | clk: imx: imx8mq: fix sys2/3_pll_out_sels | expand |
@Abel, comments? Shawn On Thu, Oct 24, 2019 at 06:57:21AM +0000, Peng Fan wrote: > From: Peng Fan <peng.fan@nxp.com> > > The current clk tree shows: > osc_25m 9 11 0 25000000 0 0 50000 > sys2_pll1_ref_sel 1 1 0 25000000 0 0 50000 > sys3_pll_out 1 1 0 25000000 0 0 50000 > sys1_pll1_ref_sel 2 2 0 25000000 0 0 50000 > sys2_pll_out 6 6 0 1000000000 0 0 50000 > > It is not correct that sys3_pll_out use sys2_pll1_ref_sel as parent, > sys2_pll_out use sys1_pll1_ref_sel as parent. > > According to the current imx_clk_sccg_pll design, it uses both > bypass1/2, however set bypass2 as 1 is not correct, because it will > make sys[x]_pll_out use wrong parent and might access wrong registers. > > So correct bypass2 to 0 and fix sys2/3_pll_out_sels. > > After fix, the tree shows: > osc_25m 10 12 0 25000000 0 0 50000 > sys3_pll1_ref_sel 1 1 0 25000000 0 0 50000 > sys3_pll_out 1 1 0 25000000 0 0 50000 > sys2_pll1_ref_sel 1 1 0 25000000 0 0 50000 > sys2_pll_out 6 6 0 1000000000 0 0 50000 > sys1_pll1_ref_sel 1 1 0 25000000 0 0 50000 > sys1_pll_out 5 5 0 800000000 0 0 50000 > > Fixes: e9dda4af685f ("clk: imx: Refactor entire sccg pll clk") > Signed-off-by: Peng Fan <peng.fan@nxp.com> > --- > drivers/clk/imx/clk-imx8mq.c | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c > index 05ece7b5da54..e17f0ebfacb0 100644 > --- a/drivers/clk/imx/clk-imx8mq.c > +++ b/drivers/clk/imx/clk-imx8mq.c > @@ -35,8 +35,8 @@ static const char * const audio_pll2_bypass_sels[] = {"audio_pll2", "audio_pll2_ > static const char * const video_pll1_bypass_sels[] = {"video_pll1", "video_pll1_ref_sel", }; > > static const char * const sys1_pll_out_sels[] = {"sys1_pll1_ref_sel", }; > -static const char * const sys2_pll_out_sels[] = {"sys1_pll1_ref_sel", "sys2_pll1_ref_sel", }; > -static const char * const sys3_pll_out_sels[] = {"sys3_pll1_ref_sel", "sys2_pll1_ref_sel", }; > +static const char * const sys2_pll_out_sels[] = {"sys2_pll1_ref_sel", }; > +static const char * const sys3_pll_out_sels[] = {"sys3_pll1_ref_sel", }; > static const char * const dram_pll_out_sels[] = {"dram_pll1_ref_sel", }; > static const char * const video2_pll_out_sels[] = {"video2_pll1_ref_sel", }; > > @@ -345,8 +345,8 @@ static int imx8mq_clocks_probe(struct platform_device *pdev) > clks[IMX8MQ_VIDEO_PLL1_OUT] = imx_clk_gate("video_pll1_out", "video_pll1_bypass", base + 0x10, 21); > > clks[IMX8MQ_SYS1_PLL_OUT] = imx_clk_sccg_pll("sys1_pll_out", sys1_pll_out_sels, ARRAY_SIZE(sys1_pll_out_sels), 0, 0, 0, base + 0x30, CLK_IS_CRITICAL); > - clks[IMX8MQ_SYS2_PLL_OUT] = imx_clk_sccg_pll("sys2_pll_out", sys2_pll_out_sels, ARRAY_SIZE(sys2_pll_out_sels), 0, 0, 1, base + 0x3c, CLK_IS_CRITICAL); > - clks[IMX8MQ_SYS3_PLL_OUT] = imx_clk_sccg_pll("sys3_pll_out", sys3_pll_out_sels, ARRAY_SIZE(sys3_pll_out_sels), 0, 0, 1, base + 0x48, CLK_IS_CRITICAL); > + clks[IMX8MQ_SYS2_PLL_OUT] = imx_clk_sccg_pll("sys2_pll_out", sys2_pll_out_sels, ARRAY_SIZE(sys2_pll_out_sels), 0, 0, 0, base + 0x3c, CLK_IS_CRITICAL); > + clks[IMX8MQ_SYS3_PLL_OUT] = imx_clk_sccg_pll("sys3_pll_out", sys3_pll_out_sels, ARRAY_SIZE(sys3_pll_out_sels), 0, 0, 0, base + 0x48, CLK_IS_CRITICAL); > clks[IMX8MQ_DRAM_PLL_OUT] = imx_clk_sccg_pll("dram_pll_out", dram_pll_out_sels, ARRAY_SIZE(dram_pll_out_sels), 0, 0, 0, base + 0x60, CLK_IS_CRITICAL); > clks[IMX8MQ_VIDEO2_PLL_OUT] = imx_clk_sccg_pll("video2_pll_out", video2_pll_out_sels, ARRAY_SIZE(video2_pll_out_sels), 0, 0, 0, base + 0x54, 0); > > -- > 2.16.4 >
> Subject: Re: [PATCH] clk: imx: imx8mq: fix sys2/3_pll_out_sels > > @Abel, comments? I have rebased patch with clk/imx and have v2 to avoid merge conflicts. https://patchwork.kernel.org/project/linux-arm-kernel/list/?submitter=166321 Thanks, Peng. > > Shawn > > On Thu, Oct 24, 2019 at 06:57:21AM +0000, Peng Fan wrote: > > From: Peng Fan <peng.fan@nxp.com> > > > > The current clk tree shows: > > osc_25m 9 11 0 > 25000000 0 0 50000 > > sys2_pll1_ref_sel 1 1 0 > 25000000 0 0 50000 > > sys3_pll_out 1 1 0 > 25000000 0 0 50000 > > sys1_pll1_ref_sel 2 2 0 > 25000000 0 0 50000 > > sys2_pll_out 6 6 0 > 1000000000 0 0 50000 > > > > It is not correct that sys3_pll_out use sys2_pll1_ref_sel as parent, > > sys2_pll_out use sys1_pll1_ref_sel as parent. > > > > According to the current imx_clk_sccg_pll design, it uses both > > bypass1/2, however set bypass2 as 1 is not correct, because it will > > make sys[x]_pll_out use wrong parent and might access wrong registers. > > > > So correct bypass2 to 0 and fix sys2/3_pll_out_sels. > > > > After fix, the tree shows: > > osc_25m 10 12 0 > 25000000 0 0 50000 > > sys3_pll1_ref_sel 1 1 0 > 25000000 0 0 50000 > > sys3_pll_out 1 1 0 > 25000000 0 0 50000 > > sys2_pll1_ref_sel 1 1 0 > 25000000 0 0 50000 > > sys2_pll_out 6 6 0 > 1000000000 0 0 50000 > > sys1_pll1_ref_sel 1 1 0 > 25000000 0 0 50000 > > sys1_pll_out 5 5 0 > 800000000 0 0 50000 > > > > Fixes: e9dda4af685f ("clk: imx: Refactor entire sccg pll clk") > > Signed-off-by: Peng Fan <peng.fan@nxp.com> > > --- > > drivers/clk/imx/clk-imx8mq.c | 8 ++++---- > > 1 file changed, 4 insertions(+), 4 deletions(-) > > > > diff --git a/drivers/clk/imx/clk-imx8mq.c > > b/drivers/clk/imx/clk-imx8mq.c index 05ece7b5da54..e17f0ebfacb0 > 100644 > > --- a/drivers/clk/imx/clk-imx8mq.c > > +++ b/drivers/clk/imx/clk-imx8mq.c > > @@ -35,8 +35,8 @@ static const char * const audio_pll2_bypass_sels[] = > > {"audio_pll2", "audio_pll2_ static const char * const > > video_pll1_bypass_sels[] = {"video_pll1", "video_pll1_ref_sel", }; > > > > static const char * const sys1_pll_out_sels[] = {"sys1_pll1_ref_sel", > > }; -static const char * const sys2_pll_out_sels[] = > > {"sys1_pll1_ref_sel", "sys2_pll1_ref_sel", }; -static const char * > > const sys3_pll_out_sels[] = {"sys3_pll1_ref_sel", "sys2_pll1_ref_sel", > > }; > > +static const char * const sys2_pll_out_sels[] = {"sys2_pll1_ref_sel", > > +}; static const char * const sys3_pll_out_sels[] = > > +{"sys3_pll1_ref_sel", }; > > static const char * const dram_pll_out_sels[] = {"dram_pll1_ref_sel", > > }; static const char * const video2_pll_out_sels[] = > > {"video2_pll1_ref_sel", }; > > > > @@ -345,8 +345,8 @@ static int imx8mq_clocks_probe(struct > platform_device *pdev) > > clks[IMX8MQ_VIDEO_PLL1_OUT] = imx_clk_gate("video_pll1_out", > > "video_pll1_bypass", base + 0x10, 21); > > > > clks[IMX8MQ_SYS1_PLL_OUT] = imx_clk_sccg_pll("sys1_pll_out", > sys1_pll_out_sels, ARRAY_SIZE(sys1_pll_out_sels), 0, 0, 0, base + 0x30, > CLK_IS_CRITICAL); > > - clks[IMX8MQ_SYS2_PLL_OUT] = imx_clk_sccg_pll("sys2_pll_out", > sys2_pll_out_sels, ARRAY_SIZE(sys2_pll_out_sels), 0, 0, 1, base + 0x3c, > CLK_IS_CRITICAL); > > - clks[IMX8MQ_SYS3_PLL_OUT] = imx_clk_sccg_pll("sys3_pll_out", > sys3_pll_out_sels, ARRAY_SIZE(sys3_pll_out_sels), 0, 0, 1, base + 0x48, > CLK_IS_CRITICAL); > > + clks[IMX8MQ_SYS2_PLL_OUT] = imx_clk_sccg_pll("sys2_pll_out", > sys2_pll_out_sels, ARRAY_SIZE(sys2_pll_out_sels), 0, 0, 0, base + 0x3c, > CLK_IS_CRITICAL); > > + clks[IMX8MQ_SYS3_PLL_OUT] = imx_clk_sccg_pll("sys3_pll_out", > > +sys3_pll_out_sels, ARRAY_SIZE(sys3_pll_out_sels), 0, 0, 0, base + > > +0x48, CLK_IS_CRITICAL); > > clks[IMX8MQ_DRAM_PLL_OUT] = imx_clk_sccg_pll("dram_pll_out", > dram_pll_out_sels, ARRAY_SIZE(dram_pll_out_sels), 0, 0, 0, base + 0x60, > CLK_IS_CRITICAL); > > clks[IMX8MQ_VIDEO2_PLL_OUT] = imx_clk_sccg_pll("video2_pll_out", > > video2_pll_out_sels, ARRAY_SIZE(video2_pll_out_sels), 0, 0, 0, base + > > 0x54, 0); > > > > -- > > 2.16.4 > >
On 19-10-28 16:53:00, Shawn Guo wrote: > @Abel, comments? > Looks good to me. Reviewed-by: Abel Vesa <abel.vesa@nxp.com> > Shawn > > On Thu, Oct 24, 2019 at 06:57:21AM +0000, Peng Fan wrote: > > From: Peng Fan <peng.fan@nxp.com> > > > > The current clk tree shows: > > osc_25m 9 11 0 25000000 0 0 50000 > > sys2_pll1_ref_sel 1 1 0 25000000 0 0 50000 > > sys3_pll_out 1 1 0 25000000 0 0 50000 > > sys1_pll1_ref_sel 2 2 0 25000000 0 0 50000 > > sys2_pll_out 6 6 0 1000000000 0 0 50000 > > > > It is not correct that sys3_pll_out use sys2_pll1_ref_sel as parent, > > sys2_pll_out use sys1_pll1_ref_sel as parent. > > > > According to the current imx_clk_sccg_pll design, it uses both > > bypass1/2, however set bypass2 as 1 is not correct, because it will > > make sys[x]_pll_out use wrong parent and might access wrong registers. > > > > So correct bypass2 to 0 and fix sys2/3_pll_out_sels. > > > > After fix, the tree shows: > > osc_25m 10 12 0 25000000 0 0 50000 > > sys3_pll1_ref_sel 1 1 0 25000000 0 0 50000 > > sys3_pll_out 1 1 0 25000000 0 0 50000 > > sys2_pll1_ref_sel 1 1 0 25000000 0 0 50000 > > sys2_pll_out 6 6 0 1000000000 0 0 50000 > > sys1_pll1_ref_sel 1 1 0 25000000 0 0 50000 > > sys1_pll_out 5 5 0 800000000 0 0 50000 > > > > Fixes: e9dda4af685f ("clk: imx: Refactor entire sccg pll clk") > > Signed-off-by: Peng Fan <peng.fan@nxp.com> > > --- > > drivers/clk/imx/clk-imx8mq.c | 8 ++++---- > > 1 file changed, 4 insertions(+), 4 deletions(-) > > > > diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c > > index 05ece7b5da54..e17f0ebfacb0 100644 > > --- a/drivers/clk/imx/clk-imx8mq.c > > +++ b/drivers/clk/imx/clk-imx8mq.c > > @@ -35,8 +35,8 @@ static const char * const audio_pll2_bypass_sels[] = {"audio_pll2", "audio_pll2_ > > static const char * const video_pll1_bypass_sels[] = {"video_pll1", "video_pll1_ref_sel", }; > > > > static const char * const sys1_pll_out_sels[] = {"sys1_pll1_ref_sel", }; > > -static const char * const sys2_pll_out_sels[] = {"sys1_pll1_ref_sel", "sys2_pll1_ref_sel", }; > > -static const char * const sys3_pll_out_sels[] = {"sys3_pll1_ref_sel", "sys2_pll1_ref_sel", }; > > +static const char * const sys2_pll_out_sels[] = {"sys2_pll1_ref_sel", }; > > +static const char * const sys3_pll_out_sels[] = {"sys3_pll1_ref_sel", }; > > static const char * const dram_pll_out_sels[] = {"dram_pll1_ref_sel", }; > > static const char * const video2_pll_out_sels[] = {"video2_pll1_ref_sel", }; > > > > @@ -345,8 +345,8 @@ static int imx8mq_clocks_probe(struct platform_device *pdev) > > clks[IMX8MQ_VIDEO_PLL1_OUT] = imx_clk_gate("video_pll1_out", "video_pll1_bypass", base + 0x10, 21); > > > > clks[IMX8MQ_SYS1_PLL_OUT] = imx_clk_sccg_pll("sys1_pll_out", sys1_pll_out_sels, ARRAY_SIZE(sys1_pll_out_sels), 0, 0, 0, base + 0x30, CLK_IS_CRITICAL); > > - clks[IMX8MQ_SYS2_PLL_OUT] = imx_clk_sccg_pll("sys2_pll_out", sys2_pll_out_sels, ARRAY_SIZE(sys2_pll_out_sels), 0, 0, 1, base + 0x3c, CLK_IS_CRITICAL); > > - clks[IMX8MQ_SYS3_PLL_OUT] = imx_clk_sccg_pll("sys3_pll_out", sys3_pll_out_sels, ARRAY_SIZE(sys3_pll_out_sels), 0, 0, 1, base + 0x48, CLK_IS_CRITICAL); > > + clks[IMX8MQ_SYS2_PLL_OUT] = imx_clk_sccg_pll("sys2_pll_out", sys2_pll_out_sels, ARRAY_SIZE(sys2_pll_out_sels), 0, 0, 0, base + 0x3c, CLK_IS_CRITICAL); > > + clks[IMX8MQ_SYS3_PLL_OUT] = imx_clk_sccg_pll("sys3_pll_out", sys3_pll_out_sels, ARRAY_SIZE(sys3_pll_out_sels), 0, 0, 0, base + 0x48, CLK_IS_CRITICAL); > > clks[IMX8MQ_DRAM_PLL_OUT] = imx_clk_sccg_pll("dram_pll_out", dram_pll_out_sels, ARRAY_SIZE(dram_pll_out_sels), 0, 0, 0, base + 0x60, CLK_IS_CRITICAL); > > clks[IMX8MQ_VIDEO2_PLL_OUT] = imx_clk_sccg_pll("video2_pll_out", video2_pll_out_sels, ARRAY_SIZE(video2_pll_out_sels), 0, 0, 0, base + 0x54, 0); > > > > -- > > 2.16.4 > >
diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c index 05ece7b5da54..e17f0ebfacb0 100644 --- a/drivers/clk/imx/clk-imx8mq.c +++ b/drivers/clk/imx/clk-imx8mq.c @@ -35,8 +35,8 @@ static const char * const audio_pll2_bypass_sels[] = {"audio_pll2", "audio_pll2_ static const char * const video_pll1_bypass_sels[] = {"video_pll1", "video_pll1_ref_sel", }; static const char * const sys1_pll_out_sels[] = {"sys1_pll1_ref_sel", }; -static const char * const sys2_pll_out_sels[] = {"sys1_pll1_ref_sel", "sys2_pll1_ref_sel", }; -static const char * const sys3_pll_out_sels[] = {"sys3_pll1_ref_sel", "sys2_pll1_ref_sel", }; +static const char * const sys2_pll_out_sels[] = {"sys2_pll1_ref_sel", }; +static const char * const sys3_pll_out_sels[] = {"sys3_pll1_ref_sel", }; static const char * const dram_pll_out_sels[] = {"dram_pll1_ref_sel", }; static const char * const video2_pll_out_sels[] = {"video2_pll1_ref_sel", }; @@ -345,8 +345,8 @@ static int imx8mq_clocks_probe(struct platform_device *pdev) clks[IMX8MQ_VIDEO_PLL1_OUT] = imx_clk_gate("video_pll1_out", "video_pll1_bypass", base + 0x10, 21); clks[IMX8MQ_SYS1_PLL_OUT] = imx_clk_sccg_pll("sys1_pll_out", sys1_pll_out_sels, ARRAY_SIZE(sys1_pll_out_sels), 0, 0, 0, base + 0x30, CLK_IS_CRITICAL); - clks[IMX8MQ_SYS2_PLL_OUT] = imx_clk_sccg_pll("sys2_pll_out", sys2_pll_out_sels, ARRAY_SIZE(sys2_pll_out_sels), 0, 0, 1, base + 0x3c, CLK_IS_CRITICAL); - clks[IMX8MQ_SYS3_PLL_OUT] = imx_clk_sccg_pll("sys3_pll_out", sys3_pll_out_sels, ARRAY_SIZE(sys3_pll_out_sels), 0, 0, 1, base + 0x48, CLK_IS_CRITICAL); + clks[IMX8MQ_SYS2_PLL_OUT] = imx_clk_sccg_pll("sys2_pll_out", sys2_pll_out_sels, ARRAY_SIZE(sys2_pll_out_sels), 0, 0, 0, base + 0x3c, CLK_IS_CRITICAL); + clks[IMX8MQ_SYS3_PLL_OUT] = imx_clk_sccg_pll("sys3_pll_out", sys3_pll_out_sels, ARRAY_SIZE(sys3_pll_out_sels), 0, 0, 0, base + 0x48, CLK_IS_CRITICAL); clks[IMX8MQ_DRAM_PLL_OUT] = imx_clk_sccg_pll("dram_pll_out", dram_pll_out_sels, ARRAY_SIZE(dram_pll_out_sels), 0, 0, 0, base + 0x60, CLK_IS_CRITICAL); clks[IMX8MQ_VIDEO2_PLL_OUT] = imx_clk_sccg_pll("video2_pll_out", video2_pll_out_sels, ARRAY_SIZE(video2_pll_out_sels), 0, 0, 0, base + 0x54, 0);