[06/10] drm/i915: Change watermark hook calling convention
diff mbox series

Message ID 20191112141503.1116-7-ville.syrjala@linux.intel.com
State New
Headers show
Series
  • drm/i915: Cleanups around .crtc_enable/disable()
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Commit Message

Ville Syrjälä Nov. 12, 2019, 2:14 p.m. UTC
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Just pass the atomic_state+crtc to the watermarks hooks. Eeasier
time for the caller when it doesn't have to think what to pass.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 32 +++++-----
 drivers/gpu/drm/i915/i915_drv.h              |  6 +-
 drivers/gpu/drm/i915/intel_pm.c              | 63 +++++++++++---------
 3 files changed, 53 insertions(+), 48 deletions(-)

Comments

Manasi Navare Nov. 14, 2019, 12:22 a.m. UTC | #1
On Tue, Nov 12, 2019 at 04:14:59PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Just pass the atomic_state+crtc to the watermarks hooks. Eeasier
> time for the caller when it doesn't have to think what to pass.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 32 +++++-----
>  drivers/gpu/drm/i915/i915_drv.h              |  6 +-
>  drivers/gpu/drm/i915/intel_pm.c              | 63 +++++++++++---------
>  3 files changed, 53 insertions(+), 48 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index ffadfd90c3cf..77b739cda053 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6177,9 +6177,8 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
>  	 * we'll continue to update watermarks the old way, if flags tell
>  	 * us to.
>  	 */
> -	if (dev_priv->display.initial_watermarks != NULL)
> -		dev_priv->display.initial_watermarks(intel_state,
> -						     pipe_config);
> +	if (dev_priv->display.initial_watermarks)
> +		dev_priv->display.initial_watermarks(intel_state, crtc);
>  	else if (pipe_config->update_wm_pre)
>  		intel_update_watermarks(crtc);
>  }
> @@ -6527,8 +6526,8 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
>  	/* update DSPCNTR to configure gamma for pipe bottom color */
>  	intel_disable_primary_plane(pipe_config);
>  
> -	if (dev_priv->display.initial_watermarks != NULL)
> -		dev_priv->display.initial_watermarks(state, pipe_config);
> +	if (dev_priv->display.initial_watermarks)
> +		dev_priv->display.initial_watermarks(state, intel_crtc);
>  	intel_enable_pipe(pipe_config);
>  
>  	if (pipe_config->has_pch_encoder)
> @@ -6671,8 +6670,8 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
>  	if (!transcoder_is_dsi(cpu_transcoder))
>  		intel_ddi_enable_transcoder_func(pipe_config);
>  
> -	if (dev_priv->display.initial_watermarks != NULL)
> -		dev_priv->display.initial_watermarks(state, pipe_config);
> +	if (dev_priv->display.initial_watermarks)
> +		dev_priv->display.initial_watermarks(state, intel_crtc);
>  
>  	if (INTEL_GEN(dev_priv) >= 11)
>  		icl_pipe_mbus_enable(intel_crtc);
> @@ -7062,7 +7061,7 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
>  	/* update DSPCNTR to configure gamma for pipe bottom color */
>  	intel_disable_primary_plane(pipe_config);
>  
> -	dev_priv->display.initial_watermarks(state, pipe_config);
> +	dev_priv->display.initial_watermarks(state, intel_crtc);

Dont we need to make sure initial_watermarks is present or !NULL before calling it
like we do in all other hooks?

Also some places we use intel_crtc vs crtc even though both are of type struct intel_crtc*,
either in this patch or another cleanup patch we should change it all to keep either crtc or
intel_crtc else there is a confusion between crtc being of type intel_crtc or drm_crtc

What do you think?
But that could be a separate change so after adding a check for if (dev_priv->display.initial_watermarks)
in valleyview_crtc_enable(),

Reviewed-by: Manasi navare <manasi.d.navare@intel.com>

Manasi

>  	intel_enable_pipe(pipe_config);
>  
>  	intel_crtc_vblank_on(pipe_config);
> @@ -7117,9 +7116,8 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
>  	/* update DSPCNTR to configure gamma for pipe bottom color */
>  	intel_disable_primary_plane(pipe_config);
>  
> -	if (dev_priv->display.initial_watermarks != NULL)
> -		dev_priv->display.initial_watermarks(state,
> -						     pipe_config);
> +	if (dev_priv->display.initial_watermarks)
> +		dev_priv->display.initial_watermarks(state, intel_crtc);
>  	else
>  		intel_update_watermarks(intel_crtc);
>  	intel_enable_pipe(pipe_config);
> @@ -14291,6 +14289,7 @@ static void commit_pipe_config(struct intel_atomic_state *state,
>  			       struct intel_crtc_state *old_crtc_state,
>  			       struct intel_crtc_state *new_crtc_state)
>  {
> +	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
>  	bool modeset = needs_modeset(new_crtc_state);
>  
> @@ -14314,8 +14313,7 @@ static void commit_pipe_config(struct intel_atomic_state *state,
>  	}
>  
>  	if (dev_priv->display.atomic_update_watermarks)
> -		dev_priv->display.atomic_update_watermarks(state,
> -							   new_crtc_state);
> +		dev_priv->display.atomic_update_watermarks(state, crtc);
>  }
>  
>  static void intel_update_crtc(struct intel_crtc *crtc,
> @@ -14419,8 +14417,7 @@ static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
>  	if (!new_crtc_state->hw.active &&
>  	    !HAS_GMCH(dev_priv) &&
>  	    dev_priv->display.initial_watermarks)
> -		dev_priv->display.initial_watermarks(state,
> -						     new_crtc_state);
> +		dev_priv->display.initial_watermarks(state, crtc);
>  }
>  
>  static void intel_trans_port_sync_modeset_disables(struct intel_atomic_state *state,
> @@ -14870,8 +14867,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>  	 */
>  	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
>  		if (dev_priv->display.optimize_watermarks)
> -			dev_priv->display.optimize_watermarks(state,
> -							      new_crtc_state);
> +			dev_priv->display.optimize_watermarks(state, crtc);
>  	}
>  
>  	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
> @@ -16826,7 +16822,7 @@ static void sanitize_watermarks(struct drm_device *dev)
>  	/* Write calculated watermark values back */
>  	for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
>  		crtc_state->wm.need_postvbl_update = true;
> -		dev_priv->display.optimize_watermarks(intel_state, crtc_state);
> +		dev_priv->display.optimize_watermarks(intel_state, crtc);
>  
>  		to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm;
>  	}
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 7e0f67babe20..00fe4ed4fb96 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -273,11 +273,11 @@ struct drm_i915_display_funcs {
>  	int (*compute_pipe_wm)(struct intel_crtc_state *crtc_state);
>  	int (*compute_intermediate_wm)(struct intel_crtc_state *crtc_state);
>  	void (*initial_watermarks)(struct intel_atomic_state *state,
> -				   struct intel_crtc_state *crtc_state);
> +				   struct intel_crtc *crtc);
>  	void (*atomic_update_watermarks)(struct intel_atomic_state *state,
> -					 struct intel_crtc_state *crtc_state);
> +					 struct intel_crtc *crtc);
>  	void (*optimize_watermarks)(struct intel_atomic_state *state,
> -				    struct intel_crtc_state *crtc_state);
> +				    struct intel_crtc *crtc);
>  	int (*compute_global_watermarks)(struct intel_atomic_state *state);
>  	void (*update_wm)(struct intel_crtc *crtc);
>  	int (*modeset_calc_cdclk)(struct intel_atomic_state *state);
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 2d389e437e87..b180342f63a6 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -1520,10 +1520,11 @@ static void g4x_program_watermarks(struct drm_i915_private *dev_priv)
>  }
>  
>  static void g4x_initial_watermarks(struct intel_atomic_state *state,
> -				   struct intel_crtc_state *crtc_state)
> +				   struct intel_crtc *crtc)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	const struct intel_crtc_state *crtc_state =
> +		intel_atomic_get_new_crtc_state(state, crtc);
>  
>  	mutex_lock(&dev_priv->wm.wm_mutex);
>  	crtc->wm.active.g4x = crtc_state->wm.g4x.intermediate;
> @@ -1532,10 +1533,11 @@ static void g4x_initial_watermarks(struct intel_atomic_state *state,
>  }
>  
>  static void g4x_optimize_watermarks(struct intel_atomic_state *state,
> -				    struct intel_crtc_state *crtc_state)
> +				    struct intel_crtc *crtc)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	const struct intel_crtc_state *crtc_state =
> +		intel_atomic_get_new_crtc_state(state, crtc);
>  
>  	if (!crtc_state->wm.need_postvbl_update)
>  		return;
> @@ -1915,11 +1917,12 @@ static int vlv_compute_pipe_wm(struct intel_crtc_state *crtc_state)
>  	(((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
>  
>  static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
> -				   struct intel_crtc_state *crtc_state)
> +				   struct intel_crtc *crtc)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	struct intel_uncore *uncore = &dev_priv->uncore;
> +	const struct intel_crtc_state *crtc_state =
> +		intel_atomic_get_new_crtc_state(state, crtc);
>  	const struct vlv_fifo_state *fifo_state =
>  		&crtc_state->wm.vlv.fifo_state;
>  	int sprite0_start, sprite1_start, fifo_size;
> @@ -2139,10 +2142,11 @@ static void vlv_program_watermarks(struct drm_i915_private *dev_priv)
>  }
>  
>  static void vlv_initial_watermarks(struct intel_atomic_state *state,
> -				   struct intel_crtc_state *crtc_state)
> +				   struct intel_crtc *crtc)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	const struct intel_crtc_state *crtc_state =
> +		intel_atomic_get_new_crtc_state(state, crtc);
>  
>  	mutex_lock(&dev_priv->wm.wm_mutex);
>  	crtc->wm.active.vlv = crtc_state->wm.vlv.intermediate;
> @@ -2151,10 +2155,11 @@ static void vlv_initial_watermarks(struct intel_atomic_state *state,
>  }
>  
>  static void vlv_optimize_watermarks(struct intel_atomic_state *state,
> -				    struct intel_crtc_state *crtc_state)
> +				    struct intel_crtc *crtc)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	const struct intel_crtc_state *crtc_state =
> +		intel_atomic_get_new_crtc_state(state, crtc);
>  
>  	if (!crtc_state->wm.need_postvbl_update)
>  		return;
> @@ -5491,11 +5496,12 @@ skl_compute_wm(struct intel_atomic_state *state)
>  }
>  
>  static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state,
> -				      struct intel_crtc_state *crtc_state)
> +				      struct intel_crtc *crtc)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> -	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> -	struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	const struct intel_crtc_state *crtc_state =
> +		intel_atomic_get_new_crtc_state(state, crtc);
> +	const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
>  	enum pipe pipe = crtc->pipe;
>  
>  	if ((state->wm_results.dirty_pipes & BIT(crtc->pipe)) == 0)
> @@ -5505,10 +5511,11 @@ static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state,
>  }
>  
>  static void skl_initial_wm(struct intel_atomic_state *state,
> -			   struct intel_crtc_state *crtc_state)
> +			   struct intel_crtc *crtc)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	const struct intel_crtc_state *crtc_state =
> +		intel_atomic_get_new_crtc_state(state, crtc);
>  	struct skl_ddb_values *results = &state->wm_results;
>  
>  	if ((results->dirty_pipes & BIT(crtc->pipe)) == 0)
> @@ -5517,7 +5524,7 @@ static void skl_initial_wm(struct intel_atomic_state *state,
>  	mutex_lock(&dev_priv->wm.wm_mutex);
>  
>  	if (crtc_state->uapi.active_changed)
> -		skl_atomic_update_crtc_wm(state, crtc_state);
> +		skl_atomic_update_crtc_wm(state, crtc);
>  
>  	mutex_unlock(&dev_priv->wm.wm_mutex);
>  }
> @@ -5573,10 +5580,11 @@ static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
>  }
>  
>  static void ilk_initial_watermarks(struct intel_atomic_state *state,
> -				   struct intel_crtc_state *crtc_state)
> +				   struct intel_crtc *crtc)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	const struct intel_crtc_state *crtc_state =
> +		intel_atomic_get_new_crtc_state(state, crtc);
>  
>  	mutex_lock(&dev_priv->wm.wm_mutex);
>  	crtc->wm.active.ilk = crtc_state->wm.ilk.intermediate;
> @@ -5585,10 +5593,11 @@ static void ilk_initial_watermarks(struct intel_atomic_state *state,
>  }
>  
>  static void ilk_optimize_watermarks(struct intel_atomic_state *state,
> -				    struct intel_crtc_state *crtc_state)
> +				    struct intel_crtc *crtc)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	const struct intel_crtc_state *crtc_state =
> +		intel_atomic_get_new_crtc_state(state, crtc);
>  
>  	if (!crtc_state->wm.need_postvbl_update)
>  		return;
> -- 
> 2.23.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Ville Syrjälä Nov. 15, 2019, 3:18 p.m. UTC | #2
On Wed, Nov 13, 2019 at 04:22:28PM -0800, Manasi Navare wrote:
> On Tue, Nov 12, 2019 at 04:14:59PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Just pass the atomic_state+crtc to the watermarks hooks. Eeasier
> > time for the caller when it doesn't have to think what to pass.
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_display.c | 32 +++++-----
> >  drivers/gpu/drm/i915/i915_drv.h              |  6 +-
> >  drivers/gpu/drm/i915/intel_pm.c              | 63 +++++++++++---------
> >  3 files changed, 53 insertions(+), 48 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > index ffadfd90c3cf..77b739cda053 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -6177,9 +6177,8 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
> >  	 * we'll continue to update watermarks the old way, if flags tell
> >  	 * us to.
> >  	 */
> > -	if (dev_priv->display.initial_watermarks != NULL)
> > -		dev_priv->display.initial_watermarks(intel_state,
> > -						     pipe_config);
> > +	if (dev_priv->display.initial_watermarks)
> > +		dev_priv->display.initial_watermarks(intel_state, crtc);
> >  	else if (pipe_config->update_wm_pre)
> >  		intel_update_watermarks(crtc);
> >  }
> > @@ -6527,8 +6526,8 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
> >  	/* update DSPCNTR to configure gamma for pipe bottom color */
> >  	intel_disable_primary_plane(pipe_config);
> >  
> > -	if (dev_priv->display.initial_watermarks != NULL)
> > -		dev_priv->display.initial_watermarks(state, pipe_config);
> > +	if (dev_priv->display.initial_watermarks)
> > +		dev_priv->display.initial_watermarks(state, intel_crtc);
> >  	intel_enable_pipe(pipe_config);
> >  
> >  	if (pipe_config->has_pch_encoder)
> > @@ -6671,8 +6670,8 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
> >  	if (!transcoder_is_dsi(cpu_transcoder))
> >  		intel_ddi_enable_transcoder_func(pipe_config);
> >  
> > -	if (dev_priv->display.initial_watermarks != NULL)
> > -		dev_priv->display.initial_watermarks(state, pipe_config);
> > +	if (dev_priv->display.initial_watermarks)
> > +		dev_priv->display.initial_watermarks(state, intel_crtc);
> >  
> >  	if (INTEL_GEN(dev_priv) >= 11)
> >  		icl_pipe_mbus_enable(intel_crtc);
> > @@ -7062,7 +7061,7 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
> >  	/* update DSPCNTR to configure gamma for pipe bottom color */
> >  	intel_disable_primary_plane(pipe_config);
> >  
> > -	dev_priv->display.initial_watermarks(state, pipe_config);
> > +	dev_priv->display.initial_watermarks(state, intel_crtc);
> 
> Dont we need to make sure initial_watermarks is present or !NULL before calling it
> like we do in all other hooks?

We know it's non-NULL here. Eventually most (if not all) of the
other checks should disappear as well. But that requires finishing
the two stage watermarks for pre-g4x.

> 
> Also some places we use intel_crtc vs crtc even though both are of type struct intel_crtc*,
> either in this patch or another cleanup patch we should change it all to keep either crtc or
> intel_crtc else there is a confusion between crtc being of type intel_crtc or drm_crtc
> 
> What do you think?
> But that could be a separate change so after adding a check for if (dev_priv->display.initial_watermarks)
> in valleyview_crtc_enable(),
> 
> Reviewed-by: Manasi navare <manasi.d.navare@intel.com>
> 
> Manasi
> 
> >  	intel_enable_pipe(pipe_config);
> >  
> >  	intel_crtc_vblank_on(pipe_config);
> > @@ -7117,9 +7116,8 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
> >  	/* update DSPCNTR to configure gamma for pipe bottom color */
> >  	intel_disable_primary_plane(pipe_config);
> >  
> > -	if (dev_priv->display.initial_watermarks != NULL)
> > -		dev_priv->display.initial_watermarks(state,
> > -						     pipe_config);
> > +	if (dev_priv->display.initial_watermarks)
> > +		dev_priv->display.initial_watermarks(state, intel_crtc);
> >  	else
> >  		intel_update_watermarks(intel_crtc);
> >  	intel_enable_pipe(pipe_config);
> > @@ -14291,6 +14289,7 @@ static void commit_pipe_config(struct intel_atomic_state *state,
> >  			       struct intel_crtc_state *old_crtc_state,
> >  			       struct intel_crtc_state *new_crtc_state)
> >  {
> > +	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
> >  	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> >  	bool modeset = needs_modeset(new_crtc_state);
> >  
> > @@ -14314,8 +14313,7 @@ static void commit_pipe_config(struct intel_atomic_state *state,
> >  	}
> >  
> >  	if (dev_priv->display.atomic_update_watermarks)
> > -		dev_priv->display.atomic_update_watermarks(state,
> > -							   new_crtc_state);
> > +		dev_priv->display.atomic_update_watermarks(state, crtc);
> >  }
> >  
> >  static void intel_update_crtc(struct intel_crtc *crtc,
> > @@ -14419,8 +14417,7 @@ static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
> >  	if (!new_crtc_state->hw.active &&
> >  	    !HAS_GMCH(dev_priv) &&
> >  	    dev_priv->display.initial_watermarks)
> > -		dev_priv->display.initial_watermarks(state,
> > -						     new_crtc_state);
> > +		dev_priv->display.initial_watermarks(state, crtc);
> >  }
> >  
> >  static void intel_trans_port_sync_modeset_disables(struct intel_atomic_state *state,
> > @@ -14870,8 +14867,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> >  	 */
> >  	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> >  		if (dev_priv->display.optimize_watermarks)
> > -			dev_priv->display.optimize_watermarks(state,
> > -							      new_crtc_state);
> > +			dev_priv->display.optimize_watermarks(state, crtc);
> >  	}
> >  
> >  	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
> > @@ -16826,7 +16822,7 @@ static void sanitize_watermarks(struct drm_device *dev)
> >  	/* Write calculated watermark values back */
> >  	for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
> >  		crtc_state->wm.need_postvbl_update = true;
> > -		dev_priv->display.optimize_watermarks(intel_state, crtc_state);
> > +		dev_priv->display.optimize_watermarks(intel_state, crtc);
> >  
> >  		to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm;
> >  	}
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 7e0f67babe20..00fe4ed4fb96 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -273,11 +273,11 @@ struct drm_i915_display_funcs {
> >  	int (*compute_pipe_wm)(struct intel_crtc_state *crtc_state);
> >  	int (*compute_intermediate_wm)(struct intel_crtc_state *crtc_state);
> >  	void (*initial_watermarks)(struct intel_atomic_state *state,
> > -				   struct intel_crtc_state *crtc_state);
> > +				   struct intel_crtc *crtc);
> >  	void (*atomic_update_watermarks)(struct intel_atomic_state *state,
> > -					 struct intel_crtc_state *crtc_state);
> > +					 struct intel_crtc *crtc);
> >  	void (*optimize_watermarks)(struct intel_atomic_state *state,
> > -				    struct intel_crtc_state *crtc_state);
> > +				    struct intel_crtc *crtc);
> >  	int (*compute_global_watermarks)(struct intel_atomic_state *state);
> >  	void (*update_wm)(struct intel_crtc *crtc);
> >  	int (*modeset_calc_cdclk)(struct intel_atomic_state *state);
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 2d389e437e87..b180342f63a6 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -1520,10 +1520,11 @@ static void g4x_program_watermarks(struct drm_i915_private *dev_priv)
> >  }
> >  
> >  static void g4x_initial_watermarks(struct intel_atomic_state *state,
> > -				   struct intel_crtc_state *crtc_state)
> > +				   struct intel_crtc *crtc)
> >  {
> > -	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> > -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > +	const struct intel_crtc_state *crtc_state =
> > +		intel_atomic_get_new_crtc_state(state, crtc);
> >  
> >  	mutex_lock(&dev_priv->wm.wm_mutex);
> >  	crtc->wm.active.g4x = crtc_state->wm.g4x.intermediate;
> > @@ -1532,10 +1533,11 @@ static void g4x_initial_watermarks(struct intel_atomic_state *state,
> >  }
> >  
> >  static void g4x_optimize_watermarks(struct intel_atomic_state *state,
> > -				    struct intel_crtc_state *crtc_state)
> > +				    struct intel_crtc *crtc)
> >  {
> > -	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> > -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > +	const struct intel_crtc_state *crtc_state =
> > +		intel_atomic_get_new_crtc_state(state, crtc);
> >  
> >  	if (!crtc_state->wm.need_postvbl_update)
> >  		return;
> > @@ -1915,11 +1917,12 @@ static int vlv_compute_pipe_wm(struct intel_crtc_state *crtc_state)
> >  	(((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
> >  
> >  static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
> > -				   struct intel_crtc_state *crtc_state)
> > +				   struct intel_crtc *crtc)
> >  {
> > -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> >  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> >  	struct intel_uncore *uncore = &dev_priv->uncore;
> > +	const struct intel_crtc_state *crtc_state =
> > +		intel_atomic_get_new_crtc_state(state, crtc);
> >  	const struct vlv_fifo_state *fifo_state =
> >  		&crtc_state->wm.vlv.fifo_state;
> >  	int sprite0_start, sprite1_start, fifo_size;
> > @@ -2139,10 +2142,11 @@ static void vlv_program_watermarks(struct drm_i915_private *dev_priv)
> >  }
> >  
> >  static void vlv_initial_watermarks(struct intel_atomic_state *state,
> > -				   struct intel_crtc_state *crtc_state)
> > +				   struct intel_crtc *crtc)
> >  {
> > -	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> > -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > +	const struct intel_crtc_state *crtc_state =
> > +		intel_atomic_get_new_crtc_state(state, crtc);
> >  
> >  	mutex_lock(&dev_priv->wm.wm_mutex);
> >  	crtc->wm.active.vlv = crtc_state->wm.vlv.intermediate;
> > @@ -2151,10 +2155,11 @@ static void vlv_initial_watermarks(struct intel_atomic_state *state,
> >  }
> >  
> >  static void vlv_optimize_watermarks(struct intel_atomic_state *state,
> > -				    struct intel_crtc_state *crtc_state)
> > +				    struct intel_crtc *crtc)
> >  {
> > -	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> > -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > +	const struct intel_crtc_state *crtc_state =
> > +		intel_atomic_get_new_crtc_state(state, crtc);
> >  
> >  	if (!crtc_state->wm.need_postvbl_update)
> >  		return;
> > @@ -5491,11 +5496,12 @@ skl_compute_wm(struct intel_atomic_state *state)
> >  }
> >  
> >  static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state,
> > -				      struct intel_crtc_state *crtc_state)
> > +				      struct intel_crtc *crtc)
> >  {
> > -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > -	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > -	struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
> > +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > +	const struct intel_crtc_state *crtc_state =
> > +		intel_atomic_get_new_crtc_state(state, crtc);
> > +	const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
> >  	enum pipe pipe = crtc->pipe;
> >  
> >  	if ((state->wm_results.dirty_pipes & BIT(crtc->pipe)) == 0)
> > @@ -5505,10 +5511,11 @@ static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state,
> >  }
> >  
> >  static void skl_initial_wm(struct intel_atomic_state *state,
> > -			   struct intel_crtc_state *crtc_state)
> > +			   struct intel_crtc *crtc)
> >  {
> > -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> >  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > +	const struct intel_crtc_state *crtc_state =
> > +		intel_atomic_get_new_crtc_state(state, crtc);
> >  	struct skl_ddb_values *results = &state->wm_results;
> >  
> >  	if ((results->dirty_pipes & BIT(crtc->pipe)) == 0)
> > @@ -5517,7 +5524,7 @@ static void skl_initial_wm(struct intel_atomic_state *state,
> >  	mutex_lock(&dev_priv->wm.wm_mutex);
> >  
> >  	if (crtc_state->uapi.active_changed)
> > -		skl_atomic_update_crtc_wm(state, crtc_state);
> > +		skl_atomic_update_crtc_wm(state, crtc);
> >  
> >  	mutex_unlock(&dev_priv->wm.wm_mutex);
> >  }
> > @@ -5573,10 +5580,11 @@ static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
> >  }
> >  
> >  static void ilk_initial_watermarks(struct intel_atomic_state *state,
> > -				   struct intel_crtc_state *crtc_state)
> > +				   struct intel_crtc *crtc)
> >  {
> > -	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> > -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > +	const struct intel_crtc_state *crtc_state =
> > +		intel_atomic_get_new_crtc_state(state, crtc);
> >  
> >  	mutex_lock(&dev_priv->wm.wm_mutex);
> >  	crtc->wm.active.ilk = crtc_state->wm.ilk.intermediate;
> > @@ -5585,10 +5593,11 @@ static void ilk_initial_watermarks(struct intel_atomic_state *state,
> >  }
> >  
> >  static void ilk_optimize_watermarks(struct intel_atomic_state *state,
> > -				    struct intel_crtc_state *crtc_state)
> > +				    struct intel_crtc *crtc)
> >  {
> > -	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> > -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > +	const struct intel_crtc_state *crtc_state =
> > +		intel_atomic_get_new_crtc_state(state, crtc);
> >  
> >  	if (!crtc_state->wm.need_postvbl_update)
> >  		return;
> > -- 
> > 2.23.0
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Patch
diff mbox series

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index ffadfd90c3cf..77b739cda053 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6177,9 +6177,8 @@  static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
 	 * we'll continue to update watermarks the old way, if flags tell
 	 * us to.
 	 */
-	if (dev_priv->display.initial_watermarks != NULL)
-		dev_priv->display.initial_watermarks(intel_state,
-						     pipe_config);
+	if (dev_priv->display.initial_watermarks)
+		dev_priv->display.initial_watermarks(intel_state, crtc);
 	else if (pipe_config->update_wm_pre)
 		intel_update_watermarks(crtc);
 }
@@ -6527,8 +6526,8 @@  static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
 	/* update DSPCNTR to configure gamma for pipe bottom color */
 	intel_disable_primary_plane(pipe_config);
 
-	if (dev_priv->display.initial_watermarks != NULL)
-		dev_priv->display.initial_watermarks(state, pipe_config);
+	if (dev_priv->display.initial_watermarks)
+		dev_priv->display.initial_watermarks(state, intel_crtc);
 	intel_enable_pipe(pipe_config);
 
 	if (pipe_config->has_pch_encoder)
@@ -6671,8 +6670,8 @@  static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
 	if (!transcoder_is_dsi(cpu_transcoder))
 		intel_ddi_enable_transcoder_func(pipe_config);
 
-	if (dev_priv->display.initial_watermarks != NULL)
-		dev_priv->display.initial_watermarks(state, pipe_config);
+	if (dev_priv->display.initial_watermarks)
+		dev_priv->display.initial_watermarks(state, intel_crtc);
 
 	if (INTEL_GEN(dev_priv) >= 11)
 		icl_pipe_mbus_enable(intel_crtc);
@@ -7062,7 +7061,7 @@  static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
 	/* update DSPCNTR to configure gamma for pipe bottom color */
 	intel_disable_primary_plane(pipe_config);
 
-	dev_priv->display.initial_watermarks(state, pipe_config);
+	dev_priv->display.initial_watermarks(state, intel_crtc);
 	intel_enable_pipe(pipe_config);
 
 	intel_crtc_vblank_on(pipe_config);
@@ -7117,9 +7116,8 @@  static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
 	/* update DSPCNTR to configure gamma for pipe bottom color */
 	intel_disable_primary_plane(pipe_config);
 
-	if (dev_priv->display.initial_watermarks != NULL)
-		dev_priv->display.initial_watermarks(state,
-						     pipe_config);
+	if (dev_priv->display.initial_watermarks)
+		dev_priv->display.initial_watermarks(state, intel_crtc);
 	else
 		intel_update_watermarks(intel_crtc);
 	intel_enable_pipe(pipe_config);
@@ -14291,6 +14289,7 @@  static void commit_pipe_config(struct intel_atomic_state *state,
 			       struct intel_crtc_state *old_crtc_state,
 			       struct intel_crtc_state *new_crtc_state)
 {
+	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 	bool modeset = needs_modeset(new_crtc_state);
 
@@ -14314,8 +14313,7 @@  static void commit_pipe_config(struct intel_atomic_state *state,
 	}
 
 	if (dev_priv->display.atomic_update_watermarks)
-		dev_priv->display.atomic_update_watermarks(state,
-							   new_crtc_state);
+		dev_priv->display.atomic_update_watermarks(state, crtc);
 }
 
 static void intel_update_crtc(struct intel_crtc *crtc,
@@ -14419,8 +14417,7 @@  static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
 	if (!new_crtc_state->hw.active &&
 	    !HAS_GMCH(dev_priv) &&
 	    dev_priv->display.initial_watermarks)
-		dev_priv->display.initial_watermarks(state,
-						     new_crtc_state);
+		dev_priv->display.initial_watermarks(state, crtc);
 }
 
 static void intel_trans_port_sync_modeset_disables(struct intel_atomic_state *state,
@@ -14870,8 +14867,7 @@  static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 	 */
 	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
 		if (dev_priv->display.optimize_watermarks)
-			dev_priv->display.optimize_watermarks(state,
-							      new_crtc_state);
+			dev_priv->display.optimize_watermarks(state, crtc);
 	}
 
 	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
@@ -16826,7 +16822,7 @@  static void sanitize_watermarks(struct drm_device *dev)
 	/* Write calculated watermark values back */
 	for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
 		crtc_state->wm.need_postvbl_update = true;
-		dev_priv->display.optimize_watermarks(intel_state, crtc_state);
+		dev_priv->display.optimize_watermarks(intel_state, crtc);
 
 		to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm;
 	}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7e0f67babe20..00fe4ed4fb96 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -273,11 +273,11 @@  struct drm_i915_display_funcs {
 	int (*compute_pipe_wm)(struct intel_crtc_state *crtc_state);
 	int (*compute_intermediate_wm)(struct intel_crtc_state *crtc_state);
 	void (*initial_watermarks)(struct intel_atomic_state *state,
-				   struct intel_crtc_state *crtc_state);
+				   struct intel_crtc *crtc);
 	void (*atomic_update_watermarks)(struct intel_atomic_state *state,
-					 struct intel_crtc_state *crtc_state);
+					 struct intel_crtc *crtc);
 	void (*optimize_watermarks)(struct intel_atomic_state *state,
-				    struct intel_crtc_state *crtc_state);
+				    struct intel_crtc *crtc);
 	int (*compute_global_watermarks)(struct intel_atomic_state *state);
 	void (*update_wm)(struct intel_crtc *crtc);
 	int (*modeset_calc_cdclk)(struct intel_atomic_state *state);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 2d389e437e87..b180342f63a6 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1520,10 +1520,11 @@  static void g4x_program_watermarks(struct drm_i915_private *dev_priv)
 }
 
 static void g4x_initial_watermarks(struct intel_atomic_state *state,
-				   struct intel_crtc_state *crtc_state)
+				   struct intel_crtc *crtc)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	const struct intel_crtc_state *crtc_state =
+		intel_atomic_get_new_crtc_state(state, crtc);
 
 	mutex_lock(&dev_priv->wm.wm_mutex);
 	crtc->wm.active.g4x = crtc_state->wm.g4x.intermediate;
@@ -1532,10 +1533,11 @@  static void g4x_initial_watermarks(struct intel_atomic_state *state,
 }
 
 static void g4x_optimize_watermarks(struct intel_atomic_state *state,
-				    struct intel_crtc_state *crtc_state)
+				    struct intel_crtc *crtc)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	const struct intel_crtc_state *crtc_state =
+		intel_atomic_get_new_crtc_state(state, crtc);
 
 	if (!crtc_state->wm.need_postvbl_update)
 		return;
@@ -1915,11 +1917,12 @@  static int vlv_compute_pipe_wm(struct intel_crtc_state *crtc_state)
 	(((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
 
 static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
-				   struct intel_crtc_state *crtc_state)
+				   struct intel_crtc *crtc)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	struct intel_uncore *uncore = &dev_priv->uncore;
+	const struct intel_crtc_state *crtc_state =
+		intel_atomic_get_new_crtc_state(state, crtc);
 	const struct vlv_fifo_state *fifo_state =
 		&crtc_state->wm.vlv.fifo_state;
 	int sprite0_start, sprite1_start, fifo_size;
@@ -2139,10 +2142,11 @@  static void vlv_program_watermarks(struct drm_i915_private *dev_priv)
 }
 
 static void vlv_initial_watermarks(struct intel_atomic_state *state,
-				   struct intel_crtc_state *crtc_state)
+				   struct intel_crtc *crtc)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	const struct intel_crtc_state *crtc_state =
+		intel_atomic_get_new_crtc_state(state, crtc);
 
 	mutex_lock(&dev_priv->wm.wm_mutex);
 	crtc->wm.active.vlv = crtc_state->wm.vlv.intermediate;
@@ -2151,10 +2155,11 @@  static void vlv_initial_watermarks(struct intel_atomic_state *state,
 }
 
 static void vlv_optimize_watermarks(struct intel_atomic_state *state,
-				    struct intel_crtc_state *crtc_state)
+				    struct intel_crtc *crtc)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	const struct intel_crtc_state *crtc_state =
+		intel_atomic_get_new_crtc_state(state, crtc);
 
 	if (!crtc_state->wm.need_postvbl_update)
 		return;
@@ -5491,11 +5496,12 @@  skl_compute_wm(struct intel_atomic_state *state)
 }
 
 static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state,
-				      struct intel_crtc_state *crtc_state)
+				      struct intel_crtc *crtc)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
-	struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	const struct intel_crtc_state *crtc_state =
+		intel_atomic_get_new_crtc_state(state, crtc);
+	const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
 	enum pipe pipe = crtc->pipe;
 
 	if ((state->wm_results.dirty_pipes & BIT(crtc->pipe)) == 0)
@@ -5505,10 +5511,11 @@  static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state,
 }
 
 static void skl_initial_wm(struct intel_atomic_state *state,
-			   struct intel_crtc_state *crtc_state)
+			   struct intel_crtc *crtc)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	const struct intel_crtc_state *crtc_state =
+		intel_atomic_get_new_crtc_state(state, crtc);
 	struct skl_ddb_values *results = &state->wm_results;
 
 	if ((results->dirty_pipes & BIT(crtc->pipe)) == 0)
@@ -5517,7 +5524,7 @@  static void skl_initial_wm(struct intel_atomic_state *state,
 	mutex_lock(&dev_priv->wm.wm_mutex);
 
 	if (crtc_state->uapi.active_changed)
-		skl_atomic_update_crtc_wm(state, crtc_state);
+		skl_atomic_update_crtc_wm(state, crtc);
 
 	mutex_unlock(&dev_priv->wm.wm_mutex);
 }
@@ -5573,10 +5580,11 @@  static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
 }
 
 static void ilk_initial_watermarks(struct intel_atomic_state *state,
-				   struct intel_crtc_state *crtc_state)
+				   struct intel_crtc *crtc)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	const struct intel_crtc_state *crtc_state =
+		intel_atomic_get_new_crtc_state(state, crtc);
 
 	mutex_lock(&dev_priv->wm.wm_mutex);
 	crtc->wm.active.ilk = crtc_state->wm.ilk.intermediate;
@@ -5585,10 +5593,11 @@  static void ilk_initial_watermarks(struct intel_atomic_state *state,
 }
 
 static void ilk_optimize_watermarks(struct intel_atomic_state *state,
-				    struct intel_crtc_state *crtc_state)
+				    struct intel_crtc *crtc)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	const struct intel_crtc_state *crtc_state =
+		intel_atomic_get_new_crtc_state(state, crtc);
 
 	if (!crtc_state->wm.need_postvbl_update)
 		return;