| Message ID | 20191218161105.30638-14-imre.deak@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/tgl: Render/media decompression support | expand |
On Wed, 2019-12-18 at 18:11 +0200, Imre Deak wrote: > From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> > > Detect the modifier corresponding to media compression to enable > display decompression for YUV and xRGB packed formats. A new modifier > is > added so that the driver can distinguish between media and render > compressed buffers. Unlike render decompression, plane 6 and plane 7 > do not > support media decompression. > > v2: Fix checkpatch warnings on code style (Lucas) > > From DK: > Separate modifier array for planes that cannot decompress media > (Ville) > > v3: Support planar formats > v4: Switch plane order > v5: > - Use format block descriptors to get CCS subsampling calculation > right > everywhere. > - Extend the plane state normal view array to accommodate 4 color > planes. > - Use helpers to convert between main and CCS planes. > > Cc: Nanley G Chery <nanley.g.chery@intel.com> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > Cc: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> > Signed-off-by: Imre Deak <imre.deak@intel.com> > --- > drivers/gpu/drm/i915/display/intel_display.c | 180 ++++++++++++++ > ---- > drivers/gpu/drm/i915/display/intel_display.h | 1 + > .../drm/i915/display/intel_display_types.h | 6 +- > drivers/gpu/drm/i915/display/intel_sprite.c | 55 ++++-- > drivers/gpu/drm/i915/i915_reg.h | 1 + > 5 files changed, 188 insertions(+), 55 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c > b/drivers/gpu/drm/i915/display/intel_display.c > index 8b36c33bb63e..1c2becf47bfd 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -1943,7 +1943,9 @@ static bool is_ccs_plane(const struct > drm_framebuffer *fb, int plane) > > static bool is_gen12_ccs_modifier(u64 modifier) > { > - return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS; > + return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS || > + modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS; > + > } > > static bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int > plane) > @@ -1976,8 +1978,7 @@ static int ccs_to_main_plane(const struct > drm_framebuffer *fb, int ccs_plane) > } > > /* Return either the main plane's CCS or - if not a CCS FB - UV > plane */ > -static int > -intel_main_to_aux_plane(const struct drm_framebuffer *fb, int > main_plane) > +int intel_main_to_aux_plane(const struct drm_framebuffer *fb, int > main_plane) > { > if (is_ccs_modifier(fb->modifier)) > return main_to_ccs_plane(fb, main_plane); > @@ -2012,6 +2013,7 @@ intel_tile_width_bytes(const struct > drm_framebuffer *fb, int color_plane) > return 128; > /* fall through */ > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: > + case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: > if (is_ccs_plane(fb, color_plane)) > return 64; > /* fall through */ > @@ -2152,6 +2154,7 @@ static unsigned int intel_surf_alignment(const > struct drm_framebuffer *fb, > return 256 * 1024; > return 0; > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: > + case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: > return 16 * 1024; > case I915_FORMAT_MOD_Y_TILED_CCS: > case I915_FORMAT_MOD_Yf_TILED_CCS: > @@ -2536,6 +2539,7 @@ static unsigned int > intel_fb_modifier_to_tiling(u64 fb_modifier) > case I915_FORMAT_MOD_Y_TILED: > case I915_FORMAT_MOD_Y_TILED_CCS: > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: > + case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: > return I915_TILING_Y; > default: > return I915_TILING_NONE; > @@ -2587,6 +2591,21 @@ static const struct drm_format_info > gen12_ccs_formats[] = { > { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2, > .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { > 1, 1 }, > .hsub = 1, .vsub = 1, .has_alpha = true }, > + { .format = DRM_FORMAT_YUYV, .num_planes = 2, > + .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { > 1, 1 }, > + .hsub = 2, .vsub = 1, .is_yuv = true }, > + { .format = DRM_FORMAT_NV12, .num_planes = 4, > + .char_per_block = { 1, 2, 1, 1 }, .block_w = { 1, 1, 4, 4 }, > .block_h = { 1, 1, 1, 1 }, > + .hsub = 2, .vsub = 2, .is_yuv = true }, > + { .format = DRM_FORMAT_P010, .num_planes = 4, > + .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, > .block_h = { 1, 1, 1, 1 }, > + .hsub = 2, .vsub = 2, .is_yuv = true }, > + { .format = DRM_FORMAT_P012, .num_planes = 4, > + .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, > .block_h = { 1, 1, 1, 1 }, > + .hsub = 2, .vsub = 2, .is_yuv = true }, > + { .format = DRM_FORMAT_P016, .num_planes = 4, > + .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, > .block_h = { 1, 1, 1, 1 }, > + .hsub = 2, .vsub = 2, .is_yuv = true }, > }; > > static const struct drm_format_info * > @@ -2613,6 +2632,7 @@ intel_get_format_info(const struct > drm_mode_fb_cmd2 *cmd) > ARRAY_SIZE(skl_ccs_formats), > cmd->pixel_format); > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: > + case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: > return lookup_format_info(gen12_ccs_formats, > ARRAY_SIZE(gen12_ccs_formats) > , > cmd->pixel_format); > @@ -2624,6 +2644,7 @@ intel_get_format_info(const struct > drm_mode_fb_cmd2 *cmd) > bool is_ccs_modifier(u64 modifier) > { > return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS || > + modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS || > modifier == I915_FORMAT_MOD_Y_TILED_CCS || > modifier == I915_FORMAT_MOD_Yf_TILED_CCS; > } > @@ -2695,7 +2716,7 @@ intel_fb_stride_alignment(const struct > drm_framebuffer *fb, int color_plane) > } > > tile_width = intel_tile_width_bytes(fb, color_plane); > - if (is_ccs_modifier(fb->modifier) && color_plane == 0) { > + if (is_ccs_modifier(fb->modifier)) { > /* > * Display WA #0531: skl,bxt,kbl,glk > * > @@ -2705,7 +2726,7 @@ intel_fb_stride_alignment(const struct > drm_framebuffer *fb, int color_plane) > * require the entire fb to accommodate that to avoid > * potential runtime errors at plane configuration > time. > */ > - if (IS_GEN(dev_priv, 9) && fb->width > 3840) > + if (IS_GEN(dev_priv, 9) && color_plane == 0 && fb- > >width > 3840) > tile_width *= 4; > /* > * The main surface pitch must be padded to a multiple > of four > @@ -2827,8 +2848,19 @@ intel_fb_plane_get_subsampling(int *hsub, int > *vsub, > > *vsub = 32; > } > + > +static void > +intel_fb_plane_dims(int *w, int *h, struct drm_framebuffer *fb, int > color_plane) > +{ > + int hsub, vsub; > + > + intel_fb_plane_get_subsampling(&hsub, &vsub, fb, color_plane); > + *w = fb->width / hsub; > + *h = fb->height / vsub; > +} > + > static int > -intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int x, int y) > +intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int ccs_plane, int > x, int y) > { > struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); > int main_plane; > @@ -2836,7 +2868,6 @@ intel_fb_check_ccs_xy(struct drm_framebuffer > *fb, int x, int y) > int tile_width, tile_height; > int ccs_x, ccs_y; > int main_x, main_y; > - int ccs_plane = 1; > > if (!is_ccs_plane(fb, ccs_plane)) > return 0; > @@ -2891,8 +2922,7 @@ intel_fill_fb_info(struct drm_i915_private > *dev_priv, > int ret; > > cpp = fb->format->cpp[i]; > - width = drm_framebuffer_plane_width(fb->width, fb, i); > - height = drm_framebuffer_plane_height(fb->height, fb, > i); > + intel_fb_plane_dims(&width, &height, fb, i); > > ret = intel_fb_offset_to_xy(&x, &y, fb, i); > if (ret) { > @@ -2901,7 +2931,7 @@ intel_fill_fb_info(struct drm_i915_private > *dev_priv, > return ret; > } > > - ret = intel_fb_check_ccs_xy(fb, x, y); > + ret = intel_fb_check_ccs_xy(fb, i, x, y); > if (ret) > return ret; > > @@ -3555,6 +3585,7 @@ static int skl_max_plane_width(const struct > drm_framebuffer *fb, > return 5120; > case I915_FORMAT_MOD_Y_TILED_CCS: > case I915_FORMAT_MOD_Yf_TILED_CCS: > + case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: > /* FIXME AUX plane? */ > case I915_FORMAT_MOD_Y_TILED: > case I915_FORMAT_MOD_Yf_TILED: > @@ -3614,10 +3645,10 @@ static int icl_max_plane_height(void) > } > > static bool skl_check_main_ccs_coordinates(struct intel_plane_state > *plane_state, > - int main_x, int main_y, u32 > main_offset) > + int main_x, int main_y, u32 > main_offset, > + int ccs_plane) > { > const struct drm_framebuffer *fb = plane_state->hw.fb; > - int ccs_plane = main_to_ccs_plane(fb, 0); > int aux_x = plane_state->color_plane[ccs_plane].x; > int aux_y = plane_state->color_plane[ccs_plane].y; > u32 aux_offset = plane_state->color_plane[ccs_plane].offset; > @@ -3723,7 +3754,8 @@ static int skl_check_main_surface(struct > intel_plane_state *plane_state) > * they match with the main surface x/y offsets. > */ > if (is_ccs_modifier(fb->modifier)) { > - while (!skl_check_main_ccs_coordinates(plane_state, x, > y, offset)) { > + while (!skl_check_main_ccs_coordinates(plane_state, x, > y, offset, > + aux_plane)) { > if (offset == 0) > break; > > @@ -3756,7 +3788,8 @@ static int skl_check_nv12_aux_surface(struct > intel_plane_state *plane_state) > { > const struct drm_framebuffer *fb = plane_state->hw.fb; > unsigned int rotation = plane_state->hw.rotation; > - int max_width = skl_max_plane_width(fb, 1, rotation); > + int uv_plane = 1; > + int max_width = skl_max_plane_width(fb, uv_plane, rotation); > int max_height = 4096; > int x = plane_state->uapi.src.x1 >> 17; > int y = plane_state->uapi.src.y1 >> 17; > @@ -3764,8 +3797,9 @@ static int skl_check_nv12_aux_surface(struct > intel_plane_state *plane_state) > int h = drm_rect_height(&plane_state->uapi.src) >> 17; > u32 offset; > > - intel_add_fb_offsets(&x, &y, plane_state, 1); > - offset = intel_plane_compute_aligned_offset(&x, &y, > plane_state, 1); > + intel_add_fb_offsets(&x, &y, plane_state, uv_plane); > + offset = intel_plane_compute_aligned_offset(&x, &y, > + plane_state, > uv_plane); > > /* FIXME not quite sure how/if these apply to the chroma plane > */ > if (w > max_width || h > max_height) { > @@ -3774,9 +3808,39 @@ static int skl_check_nv12_aux_surface(struct > intel_plane_state *plane_state) > return -EINVAL; > } > > - plane_state->color_plane[1].offset = offset; > - plane_state->color_plane[1].x = x; > - plane_state->color_plane[1].y = y; > + if (is_ccs_modifier(fb->modifier)) { > + int ccs_plane = main_to_ccs_plane(fb, uv_plane); > + int aux_offset = plane_state- > >color_plane[ccs_plane].offset; > + int alignment = intel_surf_alignment(fb, uv_plane); > + > + if (offset > aux_offset) > + offset = intel_plane_adjust_aligned_offset(&x, > &y, > + plan > e_state, > + uv_p > lane, > + offs > et, > + aux_ > offset & ~(alignment - 1)); > + > + while (!skl_check_main_ccs_coordinates(plane_state, x, > y, > + offset, > ccs_plane)) { > + if (offset == 0) > + break; > + > + offset = intel_plane_adjust_aligned_offset(&x, > &y, > + plan > e_state, > + uv_p > lane, > + offs > et, offset - alignment); > + } > + > + if (x != plane_state->color_plane[ccs_plane].x || > + y != plane_state->color_plane[ccs_plane].y) { > + DRM_DEBUG_KMS("Unable to find suitable display > surface offset due to CCS\n"); > + return -EINVAL; > + } > + } > + > + plane_state->color_plane[uv_plane].offset = offset; > + plane_state->color_plane[uv_plane].x = x; > + plane_state->color_plane[uv_plane].y = y; > > return 0; > } > @@ -3786,21 +3850,40 @@ static int skl_check_ccs_aux_surface(struct > intel_plane_state *plane_state) > const struct drm_framebuffer *fb = plane_state->hw.fb; > int src_x = plane_state->uapi.src.x1 >> 16; > int src_y = plane_state->uapi.src.y1 >> 16; > - int hsub; > - int vsub; > - int x; > - int y; > u32 offset; > + int ccs_plane; > > - intel_fb_plane_get_subsampling(&hsub, &vsub, fb, 1); > - x = src_x / hsub; > - y = src_y / vsub; > - intel_add_fb_offsets(&x, &y, plane_state, 1); > - offset = intel_plane_compute_aligned_offset(&x, &y, > plane_state, 1); > + for (ccs_plane = 0; ccs_plane < fb->format->num_planes; > ccs_plane++) { > + int main_hsub, main_vsub; > + int hsub, vsub; > + int x, y; > + > + if (!is_ccs_plane(fb, ccs_plane)) > + continue; > + > + intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, > fb, > + ccs_to_main_plane(fb, > ccs_plane)); > + intel_fb_plane_get_subsampling(&hsub, &vsub, fb, > ccs_plane); > + > + hsub *= main_hsub; > + vsub *= main_vsub; > + x = src_x / hsub; > + y = src_y / vsub; > > - plane_state->color_plane[1].offset = offset; > - plane_state->color_plane[1].x = x * hsub + src_x % hsub; > - plane_state->color_plane[1].y = y * vsub + src_y % vsub; > + intel_add_fb_offsets(&x, &y, plane_state, ccs_plane); > + > + offset = intel_plane_compute_aligned_offset(&x, &y, > + plane_state > , > + ccs_plane); > + > + plane_state->color_plane[ccs_plane].offset = offset; > + plane_state->color_plane[ccs_plane].x = (x * hsub + > + src_x % hsub) > / > + main_hsub; > + plane_state->color_plane[ccs_plane].y = (y * vsub + > + src_y % vsub) > / > + main_vsub; > + } > > return 0; > } > @@ -3809,6 +3892,7 @@ int skl_check_plane_surface(struct > intel_plane_state *plane_state) > { > const struct drm_framebuffer *fb = plane_state->hw.fb; > int ret; > + bool needs_aux = false; > > ret = intel_plane_compute_gtt(plane_state); > if (ret) > @@ -3818,22 +3902,32 @@ int skl_check_plane_surface(struct > intel_plane_state *plane_state) > return 0; > > /* > - * Handle the AUX surface first since > - * the main surface setup depends on it. > + * Handle the AUX surface first since the main surface setup > depends on > + * it. > */ > + if (is_ccs_modifier(fb->modifier)) { > + needs_aux = true; > + ret = skl_check_ccs_aux_surface(plane_state); > + if (ret) > + return ret; > + } > + > if (intel_format_info_is_yuv_semiplanar(fb->format, > fb->modifier)) { > + needs_aux = true; > ret = skl_check_nv12_aux_surface(plane_state); > if (ret) > return ret; > - } else if (is_ccs_modifier(fb->modifier)) { > - ret = skl_check_ccs_aux_surface(plane_state); > - if (ret) > - return ret; > - } else { > - plane_state->color_plane[1].offset = ~0xfff; > - plane_state->color_plane[1].x = 0; > - plane_state->color_plane[1].y = 0; > + } > + > + if (!needs_aux) { > + int i; > + > + for (i = 1; i < fb->format->num_planes; i++) { > + plane_state->color_plane[i].offset = ~0xfff; > + plane_state->color_plane[i].x = 0; > + plane_state->color_plane[i].y = 0; > + } > } > > ret = skl_check_main_surface(plane_state); > @@ -4423,6 +4517,8 @@ static u32 skl_plane_ctl_tiling(u64 > fb_modifier) > return PLANE_CTL_TILED_Y | > PLANE_CTL_RENDER_DECOMPRESSION_ENABLE | > PLANE_CTL_CLEAR_COLOR_DISABLE; > + case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: > + return PLANE_CTL_TILED_Y | > PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE; > case I915_FORMAT_MOD_Yf_TILED: > return PLANE_CTL_TILED_YF; > case I915_FORMAT_MOD_Yf_TILED_CCS: > @@ -10165,6 +10261,8 @@ skylake_get_initial_plane_config(struct > intel_crtc *crtc, > fb->modifier = INTEL_GEN(dev_priv) >= 12 ? > I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS : > I915_FORMAT_MOD_Y_TILED_CCS; > + else if (val & PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE) > + fb->modifier = > I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS; > else > fb->modifier = I915_FORMAT_MOD_Y_TILED; > break; > diff --git a/drivers/gpu/drm/i915/display/intel_display.h > b/drivers/gpu/drm/i915/display/intel_display.h > index 0fef9263cddc..b8112340773b 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.h > +++ b/drivers/gpu/drm/i915/display/intel_display.h > @@ -474,6 +474,7 @@ void intel_link_compute_m_n(u16 bpp, int nlanes, > struct intel_link_m_n *m_n, > bool constant_n, bool fec_enable); > bool is_ccs_modifier(u64 modifier); > +int intel_main_to_aux_plane(const struct drm_framebuffer *fb, int > main_plane); > void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv); > u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv, > u32 pixel_format, u64 modifier); > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h > b/drivers/gpu/drm/i915/display/intel_display_types.h > index 83ea04149b77..3cdf44fa4164 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_types.h > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h > @@ -90,8 +90,8 @@ struct intel_framebuffer { > /* for each plane in the normal GTT view */ > struct { > unsigned int x, y; > - } normal[2]; > - /* for each plane in the rotated GTT view */ > + } normal[4]; > + /* for each plane in the rotated GTT view for no-CCS formats */ > struct { > unsigned int x, y; > unsigned int pitch; /* pixels */ > @@ -555,7 +555,7 @@ struct intel_plane_state { > */ > u32 stride; > int x, y; > - } color_plane[2]; > + } color_plane[4]; > > /* plane control register */ > u32 ctl; > diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c > b/drivers/gpu/drm/i915/display/intel_sprite.c > index b7f3a1b3358f..be56b6f56411 100644 > --- a/drivers/gpu/drm/i915/display/intel_sprite.c > +++ b/drivers/gpu/drm/i915/display/intel_sprite.c > @@ -583,15 +583,16 @@ skl_program_plane(struct intel_plane *plane, > const struct drm_intel_sprite_colorkey *key = &plane_state- > >ckey; > u32 surf_addr = plane_state->color_plane[color_plane].offset; > u32 stride = skl_plane_stride(plane_state, color_plane); > - u32 aux_dist = plane_state->color_plane[1].offset - surf_addr; > - u32 aux_stride = skl_plane_stride(plane_state, 1); > + const struct drm_framebuffer *fb = plane_state->hw.fb; > + int aux_plane = intel_main_to_aux_plane(fb, color_plane); > + u32 aux_dist = plane_state->color_plane[aux_plane].offset - > surf_addr; > + u32 aux_stride = skl_plane_stride(plane_state, aux_plane); > int crtc_x = plane_state->uapi.dst.x1; > int crtc_y = plane_state->uapi.dst.y1; > u32 x = plane_state->color_plane[color_plane].x; > u32 y = plane_state->color_plane[color_plane].y; > u32 src_w = drm_rect_width(&plane_state->uapi.src) >> 16; > u32 src_h = drm_rect_height(&plane_state->uapi.src) >> 16; > - const struct drm_framebuffer *fb = plane_state->hw.fb; > u8 alpha = plane_state->hw.alpha >> 8; > u32 plane_color_ctl = 0; > unsigned long irqflags; > @@ -2106,7 +2107,8 @@ static int skl_plane_check_fb(const struct > intel_crtc_state *crtc_state, > fb->modifier == I915_FORMAT_MOD_Yf_TILED || > fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS || > fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS || > - fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS)) { > + fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS || > + fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)) { > DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID > mode\n"); > return -EINVAL; > } > @@ -2577,7 +2579,16 @@ static const u64 > skl_plane_format_modifiers_ccs[] = { > DRM_FORMAT_MOD_INVALID > }; > > -static const u64 gen12_plane_format_modifiers_ccs[] = { > +static const u64 gen12_plane_format_modifiers_mc_ccs[] = { > + I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS, > + I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS, > + I915_FORMAT_MOD_Y_TILED, > + I915_FORMAT_MOD_X_TILED, > + DRM_FORMAT_MOD_LINEAR, > + DRM_FORMAT_MOD_INVALID > +}; > + > +static const u64 gen12_plane_format_modifiers_rc_ccs[] = { > I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS, > I915_FORMAT_MOD_Y_TILED, > I915_FORMAT_MOD_X_TILED, > @@ -2742,10 +2753,21 @@ static bool > skl_plane_format_mod_supported(struct drm_plane *_plane, > } > } > > +static bool gen12_plane_supports_mc_ccs(enum plane_id plane_id) > +{ > + return plane_id < PLANE_SPRITE4; > +} > + > static bool gen12_plane_format_mod_supported(struct drm_plane > *_plane, > u32 format, u64 modifier) > { > + struct intel_plane *plane = to_intel_plane(_plane); > + > switch (modifier) { > + case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: > + if (!gen12_plane_supports_mc_ccs(plane->id)) > + return false; > + /* fall through */ > case DRM_FORMAT_MOD_LINEAR: > case I915_FORMAT_MOD_X_TILED: > case I915_FORMAT_MOD_Y_TILED: > @@ -2763,11 +2785,6 @@ static bool > gen12_plane_format_mod_supported(struct drm_plane *_plane, > if (is_ccs_modifier(modifier)) > return true; > /* fall through */ > - case DRM_FORMAT_RGB565: > - case DRM_FORMAT_XRGB2101010: > - case DRM_FORMAT_XBGR2101010: > - case DRM_FORMAT_ARGB2101010: > - case DRM_FORMAT_ABGR2101010: > case DRM_FORMAT_YUYV: > case DRM_FORMAT_YVYU: > case DRM_FORMAT_UYVY: > @@ -2776,6 +2793,14 @@ static bool > gen12_plane_format_mod_supported(struct drm_plane *_plane, > case DRM_FORMAT_P010: > case DRM_FORMAT_P012: > case DRM_FORMAT_P016: > + if (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS) > + return true; > + /* fall through */ > + case DRM_FORMAT_RGB565: > + case DRM_FORMAT_XRGB2101010: > + case DRM_FORMAT_XBGR2101010: > + case DRM_FORMAT_ARGB2101010: > + case DRM_FORMAT_ABGR2101010: > case DRM_FORMAT_XVYU2101010: > case DRM_FORMAT_C8: > case DRM_FORMAT_XBGR16161616F: > @@ -2909,6 +2934,14 @@ static const u32 *icl_get_plane_formats(struct > drm_i915_private *dev_priv, > } > } > > +static const u64 *gen12_get_plane_modifiers(enum plane_id plane_id) > +{ > + if (gen12_plane_supports_mc_ccs(plane_id)) > + return gen12_plane_format_modifiers_mc_ccs; > + else > + return gen12_plane_format_modifiers_rc_ccs; > +} > + > static bool skl_plane_has_ccs(struct drm_i915_private *dev_priv, > enum pipe pipe, enum plane_id plane_id) > { > @@ -2974,7 +3007,7 @@ skl_universal_plane_create(struct > drm_i915_private *dev_priv, > > plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id); > if (INTEL_GEN(dev_priv) >= 12) { > - modifiers = gen12_plane_format_modifiers_ccs; > + modifiers = gen12_get_plane_modifiers(plane_id); > plane_funcs = &gen12_plane_funcs; > } else { > if (plane->has_ccs) > diff --git a/drivers/gpu/drm/i915/i915_reg.h > b/drivers/gpu/drm/i915/i915_reg.h > index bbfedeb00b7f..b6dc735e85e1 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -6808,6 +6808,7 @@ enum { > #define PLANE_CTL_TILED_Y (4 << 10) > #define PLANE_CTL_TILED_YF (5 << 10) > #define PLANE_CTL_FLIP_HORIZONTAL (1 << 8) > +#define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE (1 << 4) /* > TGL+ */ > #define PLANE_CTL_ALPHA_MASK (0x3 << 4) /* > Pre-GLK */ > #define PLANE_CTL_ALPHA_DISABLE (0 << 4) > #define PLANE_CTL_ALPHA_SW_PREMULTIPLY (2 << 4)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 8b36c33bb63e..1c2becf47bfd 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -1943,7 +1943,9 @@ static bool is_ccs_plane(const struct drm_framebuffer *fb, int plane) static bool is_gen12_ccs_modifier(u64 modifier) { - return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS; + return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS || + modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS; + } static bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int plane) @@ -1976,8 +1978,7 @@ static int ccs_to_main_plane(const struct drm_framebuffer *fb, int ccs_plane) } /* Return either the main plane's CCS or - if not a CCS FB - UV plane */ -static int -intel_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane) +int intel_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane) { if (is_ccs_modifier(fb->modifier)) return main_to_ccs_plane(fb, main_plane); @@ -2012,6 +2013,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane) return 128; /* fall through */ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: + case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: if (is_ccs_plane(fb, color_plane)) return 64; /* fall through */ @@ -2152,6 +2154,7 @@ static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb, return 256 * 1024; return 0; case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: + case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: return 16 * 1024; case I915_FORMAT_MOD_Y_TILED_CCS: case I915_FORMAT_MOD_Yf_TILED_CCS: @@ -2536,6 +2539,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier) case I915_FORMAT_MOD_Y_TILED: case I915_FORMAT_MOD_Y_TILED_CCS: case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: + case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: return I915_TILING_Y; default: return I915_TILING_NONE; @@ -2587,6 +2591,21 @@ static const struct drm_format_info gen12_ccs_formats[] = { { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2, .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, .hsub = 1, .vsub = 1, .has_alpha = true }, + { .format = DRM_FORMAT_YUYV, .num_planes = 2, + .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, + .hsub = 2, .vsub = 1, .is_yuv = true }, + { .format = DRM_FORMAT_NV12, .num_planes = 4, + .char_per_block = { 1, 2, 1, 1 }, .block_w = { 1, 1, 4, 4 }, .block_h = { 1, 1, 1, 1 }, + .hsub = 2, .vsub = 2, .is_yuv = true }, + { .format = DRM_FORMAT_P010, .num_planes = 4, + .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 }, + .hsub = 2, .vsub = 2, .is_yuv = true }, + { .format = DRM_FORMAT_P012, .num_planes = 4, + .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 }, + .hsub = 2, .vsub = 2, .is_yuv = true }, + { .format = DRM_FORMAT_P016, .num_planes = 4, + .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 }, + .hsub = 2, .vsub = 2, .is_yuv = true }, }; static const struct drm_format_info * @@ -2613,6 +2632,7 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd) ARRAY_SIZE(skl_ccs_formats), cmd->pixel_format); case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: + case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: return lookup_format_info(gen12_ccs_formats, ARRAY_SIZE(gen12_ccs_formats), cmd->pixel_format); @@ -2624,6 +2644,7 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd) bool is_ccs_modifier(u64 modifier) { return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS || + modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS || modifier == I915_FORMAT_MOD_Y_TILED_CCS || modifier == I915_FORMAT_MOD_Yf_TILED_CCS; } @@ -2695,7 +2716,7 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane) } tile_width = intel_tile_width_bytes(fb, color_plane); - if (is_ccs_modifier(fb->modifier) && color_plane == 0) { + if (is_ccs_modifier(fb->modifier)) { /* * Display WA #0531: skl,bxt,kbl,glk * @@ -2705,7 +2726,7 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane) * require the entire fb to accommodate that to avoid * potential runtime errors at plane configuration time. */ - if (IS_GEN(dev_priv, 9) && fb->width > 3840) + if (IS_GEN(dev_priv, 9) && color_plane == 0 && fb->width > 3840) tile_width *= 4; /* * The main surface pitch must be padded to a multiple of four @@ -2827,8 +2848,19 @@ intel_fb_plane_get_subsampling(int *hsub, int *vsub, *vsub = 32; } + +static void +intel_fb_plane_dims(int *w, int *h, struct drm_framebuffer *fb, int color_plane) +{ + int hsub, vsub; + + intel_fb_plane_get_subsampling(&hsub, &vsub, fb, color_plane); + *w = fb->width / hsub; + *h = fb->height / vsub; +} + static int -intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int x, int y) +intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int ccs_plane, int x, int y) { struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); int main_plane; @@ -2836,7 +2868,6 @@ intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int x, int y) int tile_width, tile_height; int ccs_x, ccs_y; int main_x, main_y; - int ccs_plane = 1; if (!is_ccs_plane(fb, ccs_plane)) return 0; @@ -2891,8 +2922,7 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv, int ret; cpp = fb->format->cpp[i]; - width = drm_framebuffer_plane_width(fb->width, fb, i); - height = drm_framebuffer_plane_height(fb->height, fb, i); + intel_fb_plane_dims(&width, &height, fb, i); ret = intel_fb_offset_to_xy(&x, &y, fb, i); if (ret) { @@ -2901,7 +2931,7 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv, return ret; } - ret = intel_fb_check_ccs_xy(fb, x, y); + ret = intel_fb_check_ccs_xy(fb, i, x, y); if (ret) return ret; @@ -3555,6 +3585,7 @@ static int skl_max_plane_width(const struct drm_framebuffer *fb, return 5120; case I915_FORMAT_MOD_Y_TILED_CCS: case I915_FORMAT_MOD_Yf_TILED_CCS: + case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: /* FIXME AUX plane? */ case I915_FORMAT_MOD_Y_TILED: case I915_FORMAT_MOD_Yf_TILED: @@ -3614,10 +3645,10 @@ static int icl_max_plane_height(void) } static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state, - int main_x, int main_y, u32 main_offset) + int main_x, int main_y, u32 main_offset, + int ccs_plane) { const struct drm_framebuffer *fb = plane_state->hw.fb; - int ccs_plane = main_to_ccs_plane(fb, 0); int aux_x = plane_state->color_plane[ccs_plane].x; int aux_y = plane_state->color_plane[ccs_plane].y; u32 aux_offset = plane_state->color_plane[ccs_plane].offset; @@ -3723,7 +3754,8 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state) * they match with the main surface x/y offsets. */ if (is_ccs_modifier(fb->modifier)) { - while (!skl_check_main_ccs_coordinates(plane_state, x, y, offset)) { + while (!skl_check_main_ccs_coordinates(plane_state, x, y, offset, + aux_plane)) { if (offset == 0) break; @@ -3756,7 +3788,8 @@ static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state) { const struct drm_framebuffer *fb = plane_state->hw.fb; unsigned int rotation = plane_state->hw.rotation; - int max_width = skl_max_plane_width(fb, 1, rotation); + int uv_plane = 1; + int max_width = skl_max_plane_width(fb, uv_plane, rotation); int max_height = 4096; int x = plane_state->uapi.src.x1 >> 17; int y = plane_state->uapi.src.y1 >> 17; @@ -3764,8 +3797,9 @@ static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state) int h = drm_rect_height(&plane_state->uapi.src) >> 17; u32 offset; - intel_add_fb_offsets(&x, &y, plane_state, 1); - offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 1); + intel_add_fb_offsets(&x, &y, plane_state, uv_plane); + offset = intel_plane_compute_aligned_offset(&x, &y, + plane_state, uv_plane); /* FIXME not quite sure how/if these apply to the chroma plane */ if (w > max_width || h > max_height) { @@ -3774,9 +3808,39 @@ static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state) return -EINVAL; } - plane_state->color_plane[1].offset = offset; - plane_state->color_plane[1].x = x; - plane_state->color_plane[1].y = y; + if (is_ccs_modifier(fb->modifier)) { + int ccs_plane = main_to_ccs_plane(fb, uv_plane); + int aux_offset = plane_state->color_plane[ccs_plane].offset; + int alignment = intel_surf_alignment(fb, uv_plane); + + if (offset > aux_offset) + offset = intel_plane_adjust_aligned_offset(&x, &y, + plane_state, + uv_plane, + offset, + aux_offset & ~(alignment - 1)); + + while (!skl_check_main_ccs_coordinates(plane_state, x, y, + offset, ccs_plane)) { + if (offset == 0) + break; + + offset = intel_plane_adjust_aligned_offset(&x, &y, + plane_state, + uv_plane, + offset, offset - alignment); + } + + if (x != plane_state->color_plane[ccs_plane].x || + y != plane_state->color_plane[ccs_plane].y) { + DRM_DEBUG_KMS("Unable to find suitable display surface offset due to CCS\n"); + return -EINVAL; + } + } + + plane_state->color_plane[uv_plane].offset = offset; + plane_state->color_plane[uv_plane].x = x; + plane_state->color_plane[uv_plane].y = y; return 0; } @@ -3786,21 +3850,40 @@ static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state) const struct drm_framebuffer *fb = plane_state->hw.fb; int src_x = plane_state->uapi.src.x1 >> 16; int src_y = plane_state->uapi.src.y1 >> 16; - int hsub; - int vsub; - int x; - int y; u32 offset; + int ccs_plane; - intel_fb_plane_get_subsampling(&hsub, &vsub, fb, 1); - x = src_x / hsub; - y = src_y / vsub; - intel_add_fb_offsets(&x, &y, plane_state, 1); - offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 1); + for (ccs_plane = 0; ccs_plane < fb->format->num_planes; ccs_plane++) { + int main_hsub, main_vsub; + int hsub, vsub; + int x, y; + + if (!is_ccs_plane(fb, ccs_plane)) + continue; + + intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, fb, + ccs_to_main_plane(fb, ccs_plane)); + intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane); + + hsub *= main_hsub; + vsub *= main_vsub; + x = src_x / hsub; + y = src_y / vsub; - plane_state->color_plane[1].offset = offset; - plane_state->color_plane[1].x = x * hsub + src_x % hsub; - plane_state->color_plane[1].y = y * vsub + src_y % vsub; + intel_add_fb_offsets(&x, &y, plane_state, ccs_plane); + + offset = intel_plane_compute_aligned_offset(&x, &y, + plane_state, + ccs_plane); + + plane_state->color_plane[ccs_plane].offset = offset; + plane_state->color_plane[ccs_plane].x = (x * hsub + + src_x % hsub) / + main_hsub; + plane_state->color_plane[ccs_plane].y = (y * vsub + + src_y % vsub) / + main_vsub; + } return 0; } @@ -3809,6 +3892,7 @@ int skl_check_plane_surface(struct intel_plane_state *plane_state) { const struct drm_framebuffer *fb = plane_state->hw.fb; int ret; + bool needs_aux = false; ret = intel_plane_compute_gtt(plane_state); if (ret) @@ -3818,22 +3902,32 @@ int skl_check_plane_surface(struct intel_plane_state *plane_state) return 0; /* - * Handle the AUX surface first since - * the main surface setup depends on it. + * Handle the AUX surface first since the main surface setup depends on + * it. */ + if (is_ccs_modifier(fb->modifier)) { + needs_aux = true; + ret = skl_check_ccs_aux_surface(plane_state); + if (ret) + return ret; + } + if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) { + needs_aux = true; ret = skl_check_nv12_aux_surface(plane_state); if (ret) return ret; - } else if (is_ccs_modifier(fb->modifier)) { - ret = skl_check_ccs_aux_surface(plane_state); - if (ret) - return ret; - } else { - plane_state->color_plane[1].offset = ~0xfff; - plane_state->color_plane[1].x = 0; - plane_state->color_plane[1].y = 0; + } + + if (!needs_aux) { + int i; + + for (i = 1; i < fb->format->num_planes; i++) { + plane_state->color_plane[i].offset = ~0xfff; + plane_state->color_plane[i].x = 0; + plane_state->color_plane[i].y = 0; + } } ret = skl_check_main_surface(plane_state); @@ -4423,6 +4517,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier) return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE | PLANE_CTL_CLEAR_COLOR_DISABLE; + case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: + return PLANE_CTL_TILED_Y | PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE; case I915_FORMAT_MOD_Yf_TILED: return PLANE_CTL_TILED_YF; case I915_FORMAT_MOD_Yf_TILED_CCS: @@ -10165,6 +10261,8 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc, fb->modifier = INTEL_GEN(dev_priv) >= 12 ? I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS : I915_FORMAT_MOD_Y_TILED_CCS; + else if (val & PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE) + fb->modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS; else fb->modifier = I915_FORMAT_MOD_Y_TILED; break; diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h index 0fef9263cddc..b8112340773b 100644 --- a/drivers/gpu/drm/i915/display/intel_display.h +++ b/drivers/gpu/drm/i915/display/intel_display.h @@ -474,6 +474,7 @@ void intel_link_compute_m_n(u16 bpp, int nlanes, struct intel_link_m_n *m_n, bool constant_n, bool fec_enable); bool is_ccs_modifier(u64 modifier); +int intel_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane); void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv); u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv, u32 pixel_format, u64 modifier); diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 83ea04149b77..3cdf44fa4164 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -90,8 +90,8 @@ struct intel_framebuffer { /* for each plane in the normal GTT view */ struct { unsigned int x, y; - } normal[2]; - /* for each plane in the rotated GTT view */ + } normal[4]; + /* for each plane in the rotated GTT view for no-CCS formats */ struct { unsigned int x, y; unsigned int pitch; /* pixels */ @@ -555,7 +555,7 @@ struct intel_plane_state { */ u32 stride; int x, y; - } color_plane[2]; + } color_plane[4]; /* plane control register */ u32 ctl; diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c index b7f3a1b3358f..be56b6f56411 100644 --- a/drivers/gpu/drm/i915/display/intel_sprite.c +++ b/drivers/gpu/drm/i915/display/intel_sprite.c @@ -583,15 +583,16 @@ skl_program_plane(struct intel_plane *plane, const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; u32 surf_addr = plane_state->color_plane[color_plane].offset; u32 stride = skl_plane_stride(plane_state, color_plane); - u32 aux_dist = plane_state->color_plane[1].offset - surf_addr; - u32 aux_stride = skl_plane_stride(plane_state, 1); + const struct drm_framebuffer *fb = plane_state->hw.fb; + int aux_plane = intel_main_to_aux_plane(fb, color_plane); + u32 aux_dist = plane_state->color_plane[aux_plane].offset - surf_addr; + u32 aux_stride = skl_plane_stride(plane_state, aux_plane); int crtc_x = plane_state->uapi.dst.x1; int crtc_y = plane_state->uapi.dst.y1; u32 x = plane_state->color_plane[color_plane].x; u32 y = plane_state->color_plane[color_plane].y; u32 src_w = drm_rect_width(&plane_state->uapi.src) >> 16; u32 src_h = drm_rect_height(&plane_state->uapi.src) >> 16; - const struct drm_framebuffer *fb = plane_state->hw.fb; u8 alpha = plane_state->hw.alpha >> 8; u32 plane_color_ctl = 0; unsigned long irqflags; @@ -2106,7 +2107,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state, fb->modifier == I915_FORMAT_MOD_Yf_TILED || fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS || fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS || - fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS)) { + fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS || + fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)) { DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID mode\n"); return -EINVAL; } @@ -2577,7 +2579,16 @@ static const u64 skl_plane_format_modifiers_ccs[] = { DRM_FORMAT_MOD_INVALID }; -static const u64 gen12_plane_format_modifiers_ccs[] = { +static const u64 gen12_plane_format_modifiers_mc_ccs[] = { + I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS, + I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS, + I915_FORMAT_MOD_Y_TILED, + I915_FORMAT_MOD_X_TILED, + DRM_FORMAT_MOD_LINEAR, + DRM_FORMAT_MOD_INVALID +}; + +static const u64 gen12_plane_format_modifiers_rc_ccs[] = { I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS, I915_FORMAT_MOD_Y_TILED, I915_FORMAT_MOD_X_TILED, @@ -2742,10 +2753,21 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane, } } +static bool gen12_plane_supports_mc_ccs(enum plane_id plane_id) +{ + return plane_id < PLANE_SPRITE4; +} + static bool gen12_plane_format_mod_supported(struct drm_plane *_plane, u32 format, u64 modifier) { + struct intel_plane *plane = to_intel_plane(_plane); + switch (modifier) { + case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: + if (!gen12_plane_supports_mc_ccs(plane->id)) + return false; + /* fall through */ case DRM_FORMAT_MOD_LINEAR: case I915_FORMAT_MOD_X_TILED: case I915_FORMAT_MOD_Y_TILED: @@ -2763,11 +2785,6 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane, if (is_ccs_modifier(modifier)) return true; /* fall through */ - case DRM_FORMAT_RGB565: - case DRM_FORMAT_XRGB2101010: - case DRM_FORMAT_XBGR2101010: - case DRM_FORMAT_ARGB2101010: - case DRM_FORMAT_ABGR2101010: case DRM_FORMAT_YUYV: case DRM_FORMAT_YVYU: case DRM_FORMAT_UYVY: @@ -2776,6 +2793,14 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane, case DRM_FORMAT_P010: case DRM_FORMAT_P012: case DRM_FORMAT_P016: + if (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS) + return true; + /* fall through */ + case DRM_FORMAT_RGB565: + case DRM_FORMAT_XRGB2101010: + case DRM_FORMAT_XBGR2101010: + case DRM_FORMAT_ARGB2101010: + case DRM_FORMAT_ABGR2101010: case DRM_FORMAT_XVYU2101010: case DRM_FORMAT_C8: case DRM_FORMAT_XBGR16161616F: @@ -2909,6 +2934,14 @@ static const u32 *icl_get_plane_formats(struct drm_i915_private *dev_priv, } } +static const u64 *gen12_get_plane_modifiers(enum plane_id plane_id) +{ + if (gen12_plane_supports_mc_ccs(plane_id)) + return gen12_plane_format_modifiers_mc_ccs; + else + return gen12_plane_format_modifiers_rc_ccs; +} + static bool skl_plane_has_ccs(struct drm_i915_private *dev_priv, enum pipe pipe, enum plane_id plane_id) { @@ -2974,7 +3007,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv, plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id); if (INTEL_GEN(dev_priv) >= 12) { - modifiers = gen12_plane_format_modifiers_ccs; + modifiers = gen12_get_plane_modifiers(plane_id); plane_funcs = &gen12_plane_funcs; } else { if (plane->has_ccs) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index bbfedeb00b7f..b6dc735e85e1 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6808,6 +6808,7 @@ enum { #define PLANE_CTL_TILED_Y (4 << 10) #define PLANE_CTL_TILED_YF (5 << 10) #define PLANE_CTL_FLIP_HORIZONTAL (1 << 8) +#define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE (1 << 4) /* TGL+ */ #define PLANE_CTL_ALPHA_MASK (0x3 << 4) /* Pre-GLK */ #define PLANE_CTL_ALPHA_DISABLE (0 << 4) #define PLANE_CTL_ALPHA_SW_PREMULTIPLY (2 << 4)