| Message ID | 1579247018-6720-3-git-send-email-yash.shah@sifive.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | cacheinfo support to read no. of L2 cache ways enabled | expand |
On Thu, 16 Jan 2020 23:43:38 PST (-0800), yash.shah@sifive.com wrote: > In order to determine the number of L2 cache ways enabled at runtime, > implement a private attribute ("number_of_ways_enabled"). Reading this > attribute returns the number of enabled L2 cache ways at runtime. > > Using riscv_set_cacheinfo_ops() hook a custom function, that returns > this private attribute, to the generic ops structure which is used by > cache_get_priv_group() in cacheinfo framework. > > Signed-off-by: Yash Shah <yash.shah@sifive.com> > Reviewed-by: Anup Patel <anup@brainfault.org> > --- > drivers/soc/sifive/sifive_l2_cache.c | 38 ++++++++++++++++++++++++++++++++++++ > 1 file changed, 38 insertions(+) > > diff --git a/drivers/soc/sifive/sifive_l2_cache.c b/drivers/soc/sifive/sifive_l2_cache.c > index a506939..3fb6404 100644 > --- a/drivers/soc/sifive/sifive_l2_cache.c > +++ b/drivers/soc/sifive/sifive_l2_cache.c > @@ -9,6 +9,8 @@ > #include <linux/interrupt.h> > #include <linux/of_irq.h> > #include <linux/of_address.h> > +#include <linux/device.h> > +#include <asm/cacheinfo.h> > #include <soc/sifive/sifive_l2_cache.h> > > #define SIFIVE_L2_DIRECCFIX_LOW 0x100 > @@ -31,6 +33,7 @@ > > static void __iomem *l2_base; > static int g_irq[SIFIVE_L2_MAX_ECCINTR]; > +static struct riscv_cacheinfo_ops l2_cache_ops; > > enum { > DIR_CORR = 0, > @@ -107,6 +110,38 @@ int unregister_sifive_l2_error_notifier(struct notifier_block *nb) > } > EXPORT_SYMBOL_GPL(unregister_sifive_l2_error_notifier); > > +static int l2_largest_wayenabled(void) > +{ > + return readl(l2_base + SIFIVE_L2_WAYENABLE); > +} WayEnable is 8 bits. > + > +static ssize_t number_of_ways_enabled_show(struct device *dev, > + struct device_attribute *attr, > + char *buf) > +{ > + return sprintf(buf, "%u\n", l2_largest_wayenabled()); > +} > + > +static DEVICE_ATTR_RO(number_of_ways_enabled); > + > +static struct attribute *priv_attrs[] = { > + &dev_attr_number_of_ways_enabled.attr, > + NULL, > +}; > + > +static const struct attribute_group priv_attr_group = { > + .attrs = priv_attrs, > +}; > + > +const struct attribute_group *l2_get_priv_group(struct cacheinfo *this_leaf) > +{ > + /* We want to use private group for L2 cache only */ > + if (this_leaf->level == 2) > + return &priv_attr_group; > + else > + return NULL; > +} > + > static irqreturn_t l2_int_handler(int irq, void *device) > { > unsigned int add_h, add_l; > @@ -170,6 +205,9 @@ static int __init sifive_l2_init(void) > > l2_config_read(); > > + l2_cache_ops.get_priv_group = l2_get_priv_group; > + riscv_set_cacheinfo_ops(&l2_cache_ops); > + > #ifdef CONFIG_DEBUG_FS > setup_sifive_debug(); > #endif
> -----Original Message----- > From: Palmer Dabbelt <palmerdabbelt@google.com> > Sent: 07 February 2020 23:54 > To: Yash Shah <yash.shah@sifive.com> > Cc: Paul Walmsley ( Sifive) <paul.walmsley@sifive.com>; > aou@eecs.berkeley.edu; allison@lohutok.net; alexios.zavras@intel.com; > Greg KH <gregkh@linuxfoundation.org>; tglx@linutronix.de; bp@suse.de; > anup@brainfault.org; linux-riscv@lists.infradead.org; linux- > kernel@vger.kernel.org; Sachin Ghadi <sachin.ghadi@sifive.com>; Yash Shah > <yash.shah@sifive.com> > Subject: Re: [PATCH v4 2/2] riscv: Add support to determine no. of L2 cache > way enabled > > On Thu, 16 Jan 2020 23:43:38 PST (-0800), yash.shah@sifive.com wrote: > > In order to determine the number of L2 cache ways enabled at runtime, > > implement a private attribute ("number_of_ways_enabled"). Reading this > > attribute returns the number of enabled L2 cache ways at runtime. > > > > Using riscv_set_cacheinfo_ops() hook a custom function, that returns > > this private attribute, to the generic ops structure which is used by > > cache_get_priv_group() in cacheinfo framework. > > > > Signed-off-by: Yash Shah <yash.shah@sifive.com> > > Reviewed-by: Anup Patel <anup@brainfault.org> > > --- > > drivers/soc/sifive/sifive_l2_cache.c | 38 > > ++++++++++++++++++++++++++++++++++++ > > 1 file changed, 38 insertions(+) > > > > diff --git a/drivers/soc/sifive/sifive_l2_cache.c > > b/drivers/soc/sifive/sifive_l2_cache.c > > index a506939..3fb6404 100644 > > --- a/drivers/soc/sifive/sifive_l2_cache.c > > +++ b/drivers/soc/sifive/sifive_l2_cache.c > > @@ -9,6 +9,8 @@ > > #include <linux/interrupt.h> > > #include <linux/of_irq.h> > > #include <linux/of_address.h> > > +#include <linux/device.h> > > +#include <asm/cacheinfo.h> > > #include <soc/sifive/sifive_l2_cache.h> > > > > #define SIFIVE_L2_DIRECCFIX_LOW 0x100 @@ -31,6 +33,7 @@ > > > > static void __iomem *l2_base; > > static int g_irq[SIFIVE_L2_MAX_ECCINTR]; > > +static struct riscv_cacheinfo_ops l2_cache_ops; > > > > enum { > > DIR_CORR = 0, > > @@ -107,6 +110,38 @@ int unregister_sifive_l2_error_notifier(struct > > notifier_block *nb) } > > EXPORT_SYMBOL_GPL(unregister_sifive_l2_error_notifier); > > > > +static int l2_largest_wayenabled(void) { > > + return readl(l2_base + SIFIVE_L2_WAYENABLE); } > > WayEnable is 8 bits. Ok, will mask out and return the last 8 bits only Thanks for your comment. - Yash
diff --git a/drivers/soc/sifive/sifive_l2_cache.c b/drivers/soc/sifive/sifive_l2_cache.c index a506939..3fb6404 100644 --- a/drivers/soc/sifive/sifive_l2_cache.c +++ b/drivers/soc/sifive/sifive_l2_cache.c @@ -9,6 +9,8 @@ #include <linux/interrupt.h> #include <linux/of_irq.h> #include <linux/of_address.h> +#include <linux/device.h> +#include <asm/cacheinfo.h> #include <soc/sifive/sifive_l2_cache.h> #define SIFIVE_L2_DIRECCFIX_LOW 0x100 @@ -31,6 +33,7 @@ static void __iomem *l2_base; static int g_irq[SIFIVE_L2_MAX_ECCINTR]; +static struct riscv_cacheinfo_ops l2_cache_ops; enum { DIR_CORR = 0, @@ -107,6 +110,38 @@ int unregister_sifive_l2_error_notifier(struct notifier_block *nb) } EXPORT_SYMBOL_GPL(unregister_sifive_l2_error_notifier); +static int l2_largest_wayenabled(void) +{ + return readl(l2_base + SIFIVE_L2_WAYENABLE); +} + +static ssize_t number_of_ways_enabled_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return sprintf(buf, "%u\n", l2_largest_wayenabled()); +} + +static DEVICE_ATTR_RO(number_of_ways_enabled); + +static struct attribute *priv_attrs[] = { + &dev_attr_number_of_ways_enabled.attr, + NULL, +}; + +static const struct attribute_group priv_attr_group = { + .attrs = priv_attrs, +}; + +const struct attribute_group *l2_get_priv_group(struct cacheinfo *this_leaf) +{ + /* We want to use private group for L2 cache only */ + if (this_leaf->level == 2) + return &priv_attr_group; + else + return NULL; +} + static irqreturn_t l2_int_handler(int irq, void *device) { unsigned int add_h, add_l; @@ -170,6 +205,9 @@ static int __init sifive_l2_init(void) l2_config_read(); + l2_cache_ops.get_priv_group = l2_get_priv_group; + riscv_set_cacheinfo_ops(&l2_cache_ops); + #ifdef CONFIG_DEBUG_FS setup_sifive_debug(); #endif
In order to determine the number of L2 cache ways enabled at runtime, implement a private attribute ("number_of_ways_enabled"). Reading this attribute returns the number of enabled L2 cache ways at runtime. Using riscv_set_cacheinfo_ops() hook a custom function, that returns this private attribute, to the generic ops structure which is used by cache_get_priv_group() in cacheinfo framework. Signed-off-by: Yash Shah <yash.shah@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> --- drivers/soc/sifive/sifive_l2_cache.c | 38 ++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+)