diff mbox series

drm/i915: Enable non-contiguous pipe fusing

Message ID 20200311083632.3249-1-anshuman.gupta@intel.com (mailing list archive)
State New, archived
Headers show
Series drm/i915: Enable non-contiguous pipe fusing | expand

Commit Message

Gupta, Anshuman March 11, 2020, 8:36 a.m. UTC
Allow 3-display pipes SKU system with any combination
in INTEL_INFO pipe mask.
B.Spec:50075

changes since RFC:
- using intel_pipe_mask_is_valid() function to check integrity of
  pipe_mask. [Ville]
v2:
- simplify condition in intel_pipe_mask_is_valid(). [Ville]
v3:
- removed non-contiguous pipe fusing check. [Lucas]

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 drivers/gpu/drm/i915/intel_device_info.c | 12 +-----------
 1 file changed, 1 insertion(+), 11 deletions(-)

Comments

Gupta, Anshuman March 12, 2020, 11:08 a.m. UTC | #1
On 2020-03-11 at 10:02:47 +0000, Patchwork wrote:
> == Series Details ==
> 
> Series: drm/i915: Enable non-contiguous pipe fusing
> URL   : https://patchwork.freedesktop.org/series/74570/
> State : failure
> 
> == Summary ==
> 
> CI Bug Log - changes from CI_DRM_8113 -> Patchwork_16920
> ====================================================
> 
> Summary
> -------
> 
>   **FAILURE**
> 
>   Serious unknown changes coming with Patchwork_16920 absolutely need to be
>   verified manually.
>   
>   If you think the reported changes have nothing to do with the changes
>   introduced in Patchwork_16920, please notify your bug team to allow them
>   to document this new failure mode, which will reduce false positives in CI.
> 
>   External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16920/index.html
> 
> Possible new issues
> -------------------
> 
>   Here are the unknown changes that may have been introduced in Patchwork_16920:
> 
> ### IGT changes ###
> 
> #### Possible regressions ####
> 
>   * igt@i915_selftest@live@hangcheck:
>     - fi-apl-guc:         [PASS][1] -> [DMESG-WARN][2]
>    [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8113/fi-apl-guc/igt@i915_selftest@live@hangcheck.html
>    [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16920/fi-apl-guc/igt@i915_selftest@live@hangcheck.html
Hi Lakshmi ,

Do u have any info on above issue, is it a already known issue?

Thanks,
Anshuman Gupta.
> 
>   
> Known issues
> ------------
> 
>   Here are the changes found in Patchwork_16920 that come from known issues:
> 
> ### IGT changes ###
> 
> #### Issues hit ####
> 
>   * igt@i915_selftest@live@execlists:
>     - fi-apl-guc:         [PASS][3] -> [INCOMPLETE][4] ([fdo#103927])
>    [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8113/fi-apl-guc/igt@i915_selftest@live@execlists.html
>    [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16920/fi-apl-guc/igt@i915_selftest@live@execlists.html
> 
>   * igt@prime_vgem@basic-fence-flip:
>     - fi-tgl-y:           [PASS][5] -> [DMESG-WARN][6] ([CI#94] / [i915#402]) +1 similar issue
>    [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8113/fi-tgl-y/igt@prime_vgem@basic-fence-flip.html
>    [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16920/fi-tgl-y/igt@prime_vgem@basic-fence-flip.html
> 
>   
> #### Possible fixes ####
> 
>   * igt@gem_exec_suspend@basic-s4-devices:
>     - fi-tgl-y:           [FAIL][7] ([CI#94]) -> [PASS][8]
>    [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8113/fi-tgl-y/igt@gem_exec_suspend@basic-s4-devices.html
>    [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16920/fi-tgl-y/igt@gem_exec_suspend@basic-s4-devices.html
> 
>   * igt@kms_chamelium@hdmi-hpd-fast:
>     - fi-kbl-7500u:       [FAIL][9] ([fdo#111096] / [i915#323]) -> [PASS][10]
>    [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8113/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
>    [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16920/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
> 
>   * igt@prime_vgem@basic-read:
>     - fi-tgl-y:           [DMESG-WARN][11] ([CI#94] / [i915#402]) -> [PASS][12] +1 similar issue
>    [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8113/fi-tgl-y/igt@prime_vgem@basic-read.html
>    [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16920/fi-tgl-y/igt@prime_vgem@basic-read.html
> 
>   
>   [CI#94]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/94
>   [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
>   [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
>   [i915#323]: https://gitlab.freedesktop.org/drm/intel/issues/323
>   [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
> 
> 
> Participating hosts (47 -> 44)
> ------------------------------
> 
>   Additional (3): fi-skl-6770hq fi-kbl-7560u fi-gdg-551 
>   Missing    (6): fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus 
> 
> 
> Build changes
> -------------
> 
>   * CI: CI-20190529 -> None
>   * Linux: CI_DRM_8113 -> Patchwork_16920
> 
>   CI-20190529: 20190529
>   CI_DRM_8113: 1e2be4486f17a3f853c134097b068d000e7c6433 @ git://anongit.freedesktop.org/gfx-ci/linux
>   IGT_5505: 8973d811f3fdfb4ace4aabab2095ce0309881648 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
>   Patchwork_16920: 0514610816580178c8b380ccfb6cb00d2ce8de55 @ git://anongit.freedesktop.org/gfx-ci/linux
> 
> 
> == Linux commits ==
> 
> 051461081658 drm/i915: Enable non-contiguous pipe fusing
> 
> == Logs ==
> 
> For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16920/index.html
Vudum, Lakshminarayana March 12, 2020, 11:39 a.m. UTC | #2
Yes, that's a known issue, #656. Re-reported the results and all good now.

Thanks,
Lakshmi.
-----Original Message-----
From: Gupta, Anshuman <anshuman.gupta@intel.com> 
Sent: Thursday, March 12, 2020 1:09 PM
To: intel-gfx@lists.freedesktop.org; Vudum, Lakshminarayana <lakshminarayana.vudum@intel.com>
Subject: Re: ✗ Fi.CI.BAT: failure for drm/i915: Enable non-contiguous pipe fusing

On 2020-03-11 at 10:02:47 +0000, Patchwork wrote:
> == Series Details ==
> 
> Series: drm/i915: Enable non-contiguous pipe fusing
> URL   : https://patchwork.freedesktop.org/series/74570/
> State : failure
> 
> == Summary ==
> 
> CI Bug Log - changes from CI_DRM_8113 -> Patchwork_16920 
> ====================================================
> 
> Summary
> -------
> 
>   **FAILURE**
> 
>   Serious unknown changes coming with Patchwork_16920 absolutely need to be
>   verified manually.
>   
>   If you think the reported changes have nothing to do with the changes
>   introduced in Patchwork_16920, please notify your bug team to allow them
>   to document this new failure mode, which will reduce false positives in CI.
> 
>   External URL: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16920/index.html
> 
> Possible new issues
> -------------------
> 
>   Here are the unknown changes that may have been introduced in Patchwork_16920:
> 
> ### IGT changes ###
> 
> #### Possible regressions ####
> 
>   * igt@i915_selftest@live@hangcheck:
>     - fi-apl-guc:         [PASS][1] -> [DMESG-WARN][2]
>    [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8113/fi-apl-guc/igt@i915_selftest@live@hangcheck.html
>    [2]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16920/fi-apl-guc/ig
> t@i915_selftest@live@hangcheck.html
Hi Lakshmi ,

Do u have any info on above issue, is it a already known issue?

Thanks,
Anshuman Gupta.
> 
>   
> Known issues
> ------------
> 
>   Here are the changes found in Patchwork_16920 that come from known issues:
> 
> ### IGT changes ###
> 
> #### Issues hit ####
> 
>   * igt@i915_selftest@live@execlists:
>     - fi-apl-guc:         [PASS][3] -> [INCOMPLETE][4] ([fdo#103927])
>    [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8113/fi-apl-guc/igt@i915_selftest@live@execlists.html
>    [4]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16920/fi-apl-guc/ig
> t@i915_selftest@live@execlists.html
> 
>   * igt@prime_vgem@basic-fence-flip:
>     - fi-tgl-y:           [PASS][5] -> [DMESG-WARN][6] ([CI#94] / [i915#402]) +1 similar issue
>    [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8113/fi-tgl-y/igt@prime_vgem@basic-fence-flip.html
>    [6]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16920/fi-tgl-y/igt@
> prime_vgem@basic-fence-flip.html
> 
>   
> #### Possible fixes ####
> 
>   * igt@gem_exec_suspend@basic-s4-devices:
>     - fi-tgl-y:           [FAIL][7] ([CI#94]) -> [PASS][8]
>    [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8113/fi-tgl-y/igt@gem_exec_suspend@basic-s4-devices.html
>    [8]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16920/fi-tgl-y/igt@
> gem_exec_suspend@basic-s4-devices.html
> 
>   * igt@kms_chamelium@hdmi-hpd-fast:
>     - fi-kbl-7500u:       [FAIL][9] ([fdo#111096] / [i915#323]) -> [PASS][10]
>    [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8113/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
>    [10]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16920/fi-kbl-7500u/
> igt@kms_chamelium@hdmi-hpd-fast.html
> 
>   * igt@prime_vgem@basic-read:
>     - fi-tgl-y:           [DMESG-WARN][11] ([CI#94] / [i915#402]) -> [PASS][12] +1 similar issue
>    [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8113/fi-tgl-y/igt@prime_vgem@basic-read.html
>    [12]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16920/fi-tgl-y/igt@
> prime_vgem@basic-read.html
> 
>   
>   [CI#94]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/94
>   [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
>   [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
>   [i915#323]: https://gitlab.freedesktop.org/drm/intel/issues/323
>   [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
> 
> 
> Participating hosts (47 -> 44)
> ------------------------------
> 
>   Additional (3): fi-skl-6770hq fi-kbl-7560u fi-gdg-551 
>   Missing    (6): fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus 
> 
> 
> Build changes
> -------------
> 
>   * CI: CI-20190529 -> None
>   * Linux: CI_DRM_8113 -> Patchwork_16920
> 
>   CI-20190529: 20190529
>   CI_DRM_8113: 1e2be4486f17a3f853c134097b068d000e7c6433 @ git://anongit.freedesktop.org/gfx-ci/linux
>   IGT_5505: 8973d811f3fdfb4ace4aabab2095ce0309881648 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
>   Patchwork_16920: 0514610816580178c8b380ccfb6cb00d2ce8de55 @ 
> git://anongit.freedesktop.org/gfx-ci/linux
> 
> 
> == Linux commits ==
> 
> 051461081658 drm/i915: Enable non-contiguous pipe fusing
> 
> == Logs ==
> 
> For more details see: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16920/index.html
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Lucas De Marchi March 13, 2020, 7:39 a.m. UTC | #3
On Wed, Mar 11, 2020 at 02:06:32PM +0530, Anshuman Gupta wrote:
>Allow 3-display pipes SKU system with any combination
>in INTEL_INFO pipe mask.
>B.Spec:50075
>
>changes since RFC:
>- using intel_pipe_mask_is_valid() function to check integrity of
>  pipe_mask. [Ville]
>v2:
>- simplify condition in intel_pipe_mask_is_valid(). [Ville]
>v3:
>- removed non-contiguous pipe fusing check. [Lucas]

I'd also say in the commit message that the support for non-contiguous
pipe fusing is *already* supported in the driver. So this check here
doesn't make sense anymore and since it's an unlike condition we
can just stop checking.

Aside from commit message update,

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>

Lucas De Marchi

>
>Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
>---
> drivers/gpu/drm/i915/intel_device_info.c | 12 +-----------
> 1 file changed, 1 insertion(+), 11 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
>index d7fe12734db8..9ff89e142ff1 100644
>--- a/drivers/gpu/drm/i915/intel_device_info.c
>+++ b/drivers/gpu/drm/i915/intel_device_info.c
>@@ -998,17 +998,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
> 		    (dfsm & TGL_DFSM_PIPE_D_DISABLE))
> 			enabled_mask &= ~BIT(PIPE_D);
>
>-		/*
>-		 * At least one pipe should be enabled and if there are
>-		 * disabled pipes, they should be the last ones, with no holes
>-		 * in the mask.
>-		 */
>-		if (enabled_mask == 0 || !is_power_of_2(enabled_mask + 1))
>-			drm_err(&dev_priv->drm,
>-				"invalid pipe fuse configuration: enabled_mask=0x%x\n",
>-				enabled_mask);
>-		else
>-			info->pipe_mask = enabled_mask;
>+		info->pipe_mask = enabled_mask;
>
> 		if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE)
> 			info->display.has_hdcp = 0;
>-- 
>2.25.1
>
Ville Syrjälä March 18, 2020, 4:48 p.m. UTC | #4
On Fri, Mar 13, 2020 at 12:39:17AM -0700, Lucas De Marchi wrote:
> On Wed, Mar 11, 2020 at 02:06:32PM +0530, Anshuman Gupta wrote:
> >Allow 3-display pipes SKU system with any combination
> >in INTEL_INFO pipe mask.
> >B.Spec:50075
> >
> >changes since RFC:
> >- using intel_pipe_mask_is_valid() function to check integrity of
> >  pipe_mask. [Ville]
> >v2:
> >- simplify condition in intel_pipe_mask_is_valid(). [Ville]
> >v3:
> >- removed non-contiguous pipe fusing check. [Lucas]
> 
> I'd also say in the commit message that the support for non-contiguous
> pipe fusing is *already* supported in the driver. So this check here
> doesn't make sense anymore and since it's an unlike condition we
> can just stop checking.

BTW I think we still have those crtc index==pipe asserts in the code
somewhere. Now that all the (known) assumptions have been fixed we can
remove the WARNs.

> 
> Aside from commit message update,
> 
> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
> 
> Lucas De Marchi
> 
> >
> >Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> >Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> >---
> > drivers/gpu/drm/i915/intel_device_info.c | 12 +-----------
> > 1 file changed, 1 insertion(+), 11 deletions(-)
> >
> >diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> >index d7fe12734db8..9ff89e142ff1 100644
> >--- a/drivers/gpu/drm/i915/intel_device_info.c
> >+++ b/drivers/gpu/drm/i915/intel_device_info.c
> >@@ -998,17 +998,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
> > 		    (dfsm & TGL_DFSM_PIPE_D_DISABLE))
> > 			enabled_mask &= ~BIT(PIPE_D);
> >
> >-		/*
> >-		 * At least one pipe should be enabled and if there are
> >-		 * disabled pipes, they should be the last ones, with no holes
> >-		 * in the mask.
> >-		 */
> >-		if (enabled_mask == 0 || !is_power_of_2(enabled_mask + 1))
> >-			drm_err(&dev_priv->drm,
> >-				"invalid pipe fuse configuration: enabled_mask=0x%x\n",
> >-				enabled_mask);
> >-		else
> >-			info->pipe_mask = enabled_mask;
> >+		info->pipe_mask = enabled_mask;
> >
> > 		if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE)
> > 			info->display.has_hdcp = 0;
> >-- 
> >2.25.1
> >
Gupta, Anshuman March 19, 2020, 7:53 a.m. UTC | #5
On 2020-03-18 at 18:48:27 +0200, Ville Syrjälä wrote:
> On Fri, Mar 13, 2020 at 12:39:17AM -0700, Lucas De Marchi wrote:
> > On Wed, Mar 11, 2020 at 02:06:32PM +0530, Anshuman Gupta wrote:
> > >Allow 3-display pipes SKU system with any combination
> > >in INTEL_INFO pipe mask.
> > >B.Spec:50075
> > >
> > >changes since RFC:
> > >- using intel_pipe_mask_is_valid() function to check integrity of
> > >  pipe_mask. [Ville]
> > >v2:
> > >- simplify condition in intel_pipe_mask_is_valid(). [Ville]
> > >v3:
> > >- removed non-contiguous pipe fusing check. [Lucas]
> > 
> > I'd also say in the commit message that the support for non-contiguous
> > pipe fusing is *already* supported in the driver. So this check here
> > doesn't make sense anymore and since it's an unlike condition we
> > can just stop checking.
> 
> BTW I think we still have those crtc index==pipe asserts in the code
> somewhere. Now that all the (known) assumptions have been fixed we can
> remove the WARNs.
yes we still have drm_WARN_ON(&dev_priv->drm, drm_crtc_index(&crtc->base) != crtc->pipe)
in intel_crtc_init.
AFAIU the idea was to have the WARN_ON to know that we are running a broken driver
(if there any unknown assumption is still left out).
Please correct me if i am wrong here, if it is required to remove the above WARN_ON, i will send
a patch for it. 
Thanks,
Anshuman Gupta.
> 
> > 
> > Aside from commit message update,
> > 
> > Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > 
> > Lucas De Marchi
> > 
> > >
> > >Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > >Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> > >Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> > >---
> > > drivers/gpu/drm/i915/intel_device_info.c | 12 +-----------
> > > 1 file changed, 1 insertion(+), 11 deletions(-)
> > >
> > >diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> > >index d7fe12734db8..9ff89e142ff1 100644
> > >--- a/drivers/gpu/drm/i915/intel_device_info.c
> > >+++ b/drivers/gpu/drm/i915/intel_device_info.c
> > >@@ -998,17 +998,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
> > > 		    (dfsm & TGL_DFSM_PIPE_D_DISABLE))
> > > 			enabled_mask &= ~BIT(PIPE_D);
> > >
> > >-		/*
> > >-		 * At least one pipe should be enabled and if there are
> > >-		 * disabled pipes, they should be the last ones, with no holes
> > >-		 * in the mask.
> > >-		 */
> > >-		if (enabled_mask == 0 || !is_power_of_2(enabled_mask + 1))
> > >-			drm_err(&dev_priv->drm,
> > >-				"invalid pipe fuse configuration: enabled_mask=0x%x\n",
> > >-				enabled_mask);
> > >-		else
> > >-			info->pipe_mask = enabled_mask;
> > >+		info->pipe_mask = enabled_mask;
> > >
> > > 		if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE)
> > > 			info->display.has_hdcp = 0;
> > >-- 
> > >2.25.1
> > >
> 
> -- 
> Ville Syrjälä
> Intel
Ville Syrjälä March 19, 2020, 4:06 p.m. UTC | #6
On Thu, Mar 19, 2020 at 01:23:18PM +0530, Anshuman Gupta wrote:
> On 2020-03-18 at 18:48:27 +0200, Ville Syrjälä wrote:
> > On Fri, Mar 13, 2020 at 12:39:17AM -0700, Lucas De Marchi wrote:
> > > On Wed, Mar 11, 2020 at 02:06:32PM +0530, Anshuman Gupta wrote:
> > > >Allow 3-display pipes SKU system with any combination
> > > >in INTEL_INFO pipe mask.
> > > >B.Spec:50075
> > > >
> > > >changes since RFC:
> > > >- using intel_pipe_mask_is_valid() function to check integrity of
> > > >  pipe_mask. [Ville]
> > > >v2:
> > > >- simplify condition in intel_pipe_mask_is_valid(). [Ville]
> > > >v3:
> > > >- removed non-contiguous pipe fusing check. [Lucas]
> > > 
> > > I'd also say in the commit message that the support for non-contiguous
> > > pipe fusing is *already* supported in the driver. So this check here
> > > doesn't make sense anymore and since it's an unlike condition we
> > > can just stop checking.
> > 
> > BTW I think we still have those crtc index==pipe asserts in the code
> > somewhere. Now that all the (known) assumptions have been fixed we can
> > remove the WARNs.
> yes we still have drm_WARN_ON(&dev_priv->drm, drm_crtc_index(&crtc->base) != crtc->pipe)
> in intel_crtc_init.
> AFAIU the idea was to have the WARN_ON to know that we are running a broken driver
> (if there any unknown assumption is still left out).

Unknown assumptions are by definition unknown. The WARN will not help
with those.
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index d7fe12734db8..9ff89e142ff1 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -998,17 +998,7 @@  void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
 		    (dfsm & TGL_DFSM_PIPE_D_DISABLE))
 			enabled_mask &= ~BIT(PIPE_D);
 
-		/*
-		 * At least one pipe should be enabled and if there are
-		 * disabled pipes, they should be the last ones, with no holes
-		 * in the mask.
-		 */
-		if (enabled_mask == 0 || !is_power_of_2(enabled_mask + 1))
-			drm_err(&dev_priv->drm,
-				"invalid pipe fuse configuration: enabled_mask=0x%x\n",
-				enabled_mask);
-		else
-			info->pipe_mask = enabled_mask;
+		info->pipe_mask = enabled_mask;
 
 		if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE)
 			info->display.has_hdcp = 0;