| Message ID | 20200514123838.3017-1-ville.syrjala@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v2,1/3] drm/i915: Fix 400 MHz FSB readout on elk | expand |
Quoting Ville Syrjala (2020-05-14 13:38:36) > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Looks like elk redefines some of the CLKCFG FSB values to > make room for 400 MHz FSB. The setting overlaps with one of > the 266MHz settings (which is even documented in the ctg docs, > and cofirmed to be correct on my ctg). So we limit the special > case to elk only. > > Though it might also be that we have some kind of desktop vs. > mobile difference going on here as eg. both g35 and elk > use 0x0 for the 266 MHz setting, vs. 0x6 used by ctg). The > g35 doesn't let me select 400MHz for the FSB strap so can't > confirm which way it would go here. But anyways as it seems > only elk has the 400MHz option we shouldn't lose anything > by limiting the special case to it alone. > > My earlier experiments on this appear to have been nonsense as > the comment I added claims that FSB strap of 400MHz results in > a value of 0x4, but I've now retested it and I definitely get a > value of 0x6 instead. So let's remove that bogus comment. > > v2: s/_ELK/_ALT/ in the define in anticipation of a full > mobile vs. desktop CLKCFG split > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Acked-by: Chris Wilson <chris@chris-wilson.co.uk> -Chris
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 979a0241fdcb..c17cf611625c 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -2705,8 +2705,13 @@ static int g4x_hrawclk(struct drm_i915_private *dev_priv) u32 clkcfg; /* hrawclock is 1/4 the FSB frequency */ - clkcfg = intel_de_read(dev_priv, CLKCFG); - switch (clkcfg & CLKCFG_FSB_MASK) { + clkcfg = intel_de_read(dev_priv, CLKCFG) & CLKCFG_FSB_MASK; + + /* ELK seems to redefine some of the values */ + if (IS_G45(dev_priv) && clkcfg == CLKCFG_FSB_1600_ALT) + return 400000; + + switch (clkcfg) { case CLKCFG_FSB_400: return 100000; case CLKCFG_FSB_533: diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 6c076a24eb82..10187780e06c 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3775,12 +3775,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */ #define CLKCFG_FSB_1067_ALT (0 << 0) /* hrawclk 266 */ #define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */ -/* - * Note that on at least on ELK the below value is reported for both - * 333 and 400 MHz BIOS FSB setting, but given that the gmch datasheet - * lists only 200/266/333 MHz FSB as supported let's decode it as 333 MHz. - */ #define CLKCFG_FSB_1333_ALT (4 << 0) /* hrawclk 333 */ +#define CLKCFG_FSB_1600_ALT (6 << 0) /* hrawclk 400 */ #define CLKCFG_FSB_MASK (7 << 0) #define CLKCFG_MEM_533 (1 << 4) #define CLKCFG_MEM_667 (2 << 4)