Message ID | 122b78825b077e4dfd39b444d3a46fe894a7804c.1593547870.git.alistair.francis@wdc.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | A few RISC-V fixes | expand |
On 2020/7/1 4:12, Alistair Francis wrote: > Commit 5d971f9e672507210e77d020d89e0e89165c8fc9 > "memory: Revert "memory: accept mismatching sizes in > memory_region_access_valid"" broke most RISC-V boards as they do 64 bit > accesses to the CLINT and QEMU would trigger a fault. Fix this failure > by allowing 8 byte accesses. > > Signed-off-by: Alistair Francis <alistair.francis@wdc.com> > --- > hw/riscv/sifive_clint.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/hw/riscv/sifive_clint.c b/hw/riscv/sifive_clint.c > index b11ffa0edc..669c21adc2 100644 > --- a/hw/riscv/sifive_clint.c > +++ b/hw/riscv/sifive_clint.c > @@ -181,7 +181,7 @@ static const MemoryRegionOps sifive_clint_ops = { > .endianness = DEVICE_LITTLE_ENDIAN, > .valid = { > .min_access_size = 4, > - .max_access_size = 4 > + .max_access_size = 8 > } > }; > Reviewed-by: LIU Zhiwei<zhiwei_liu@c-sky.com>
On Tue, Jun 30, 2020 at 5:19 PM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote: > > > > On 2020/7/1 4:12, Alistair Francis wrote: > > Commit 5d971f9e672507210e77d020d89e0e89165c8fc9 > > "memory: Revert "memory: accept mismatching sizes in > > memory_region_access_valid"" broke most RISC-V boards as they do 64 bit > > accesses to the CLINT and QEMU would trigger a fault. Fix this failure > > by allowing 8 byte accesses. > > > > Signed-off-by: Alistair Francis <alistair.francis@wdc.com> > > --- > > hw/riscv/sifive_clint.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/hw/riscv/sifive_clint.c b/hw/riscv/sifive_clint.c > > index b11ffa0edc..669c21adc2 100644 > > --- a/hw/riscv/sifive_clint.c > > +++ b/hw/riscv/sifive_clint.c > > @@ -181,7 +181,7 @@ static const MemoryRegionOps sifive_clint_ops = { > > .endianness = DEVICE_LITTLE_ENDIAN, > > .valid = { > > .min_access_size = 4, > > - .max_access_size = 4 > > + .max_access_size = 8 > > } > > }; > > > > Reviewed-by: LIU Zhiwei<zhiwei_liu@c-sky.com> Thanks for the review. As most RISC-V machines are broken without this patch I have applied it to my next PR. Alistair > >
On 6/30/20 10:12 PM, Alistair Francis wrote: > Commit 5d971f9e672507210e77d020d89e0e89165c8fc9 > "memory: Revert "memory: accept mismatching sizes in > memory_region_access_valid"" broke most RISC-V boards as they do 64 bit > accesses to the CLINT and QEMU would trigger a fault. Fix this failure > by allowing 8 byte accesses. > Fixes: 5d971f9e67 (Revert "accept mismatching sizes in access_valid") Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> > Signed-off-by: Alistair Francis <alistair.francis@wdc.com> > --- > hw/riscv/sifive_clint.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/hw/riscv/sifive_clint.c b/hw/riscv/sifive_clint.c > index b11ffa0edc..669c21adc2 100644 > --- a/hw/riscv/sifive_clint.c > +++ b/hw/riscv/sifive_clint.c > @@ -181,7 +181,7 @@ static const MemoryRegionOps sifive_clint_ops = { > .endianness = DEVICE_LITTLE_ENDIAN, > .valid = { > .min_access_size = 4, > - .max_access_size = 4 > + .max_access_size = 8 > } > }; > >
diff --git a/hw/riscv/sifive_clint.c b/hw/riscv/sifive_clint.c index b11ffa0edc..669c21adc2 100644 --- a/hw/riscv/sifive_clint.c +++ b/hw/riscv/sifive_clint.c @@ -181,7 +181,7 @@ static const MemoryRegionOps sifive_clint_ops = { .endianness = DEVICE_LITTLE_ENDIAN, .valid = { .min_access_size = 4, - .max_access_size = 4 + .max_access_size = 8 } };
Commit 5d971f9e672507210e77d020d89e0e89165c8fc9 "memory: Revert "memory: accept mismatching sizes in memory_region_access_valid"" broke most RISC-V boards as they do 64 bit accesses to the CLINT and QEMU would trigger a fault. Fix this failure by allowing 8 byte accesses. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> --- hw/riscv/sifive_clint.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)