| Message ID | 1594088183-7187-5-git-send-email-cathy.zhang@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Expose new features for intel processor | expand |
diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index e603aeb..dcf48cc 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -342,7 +342,7 @@ void kvm_set_cpu_caps(void) F(AVX512_4VNNIW) | F(AVX512_4FMAPS) | F(SPEC_CTRL) | F(SPEC_CTRL_SSBD) | F(ARCH_CAPABILITIES) | F(INTEL_STIBP) | F(MD_CLEAR) | F(AVX512_VP2INTERSECT) | F(FSRM) | - F(SERIALIZE) + F(SERIALIZE) | F(TSX_LDTRK) ); /* TSC_ADJUST and ARCH_CAPABILITIES are emulated in software. */
TSX Suspend Load Address Tracking is supported by intel processors, like Sapphire Rapids. Expose it in KVM supported cpuid. Signed-off-by: Cathy Zhang <cathy.zhang@intel.com> --- arch/x86/kvm/cpuid.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)