diff mbox series

drm/i915: Correct location of Wa_1408615072

Message ID 20200710213246.222179-1-John.C.Harrison@Intel.com (mailing list archive)
State New, archived
Headers show
Series drm/i915: Correct location of Wa_1408615072 | expand

Commit Message

John Harrison July 10, 2020, 9:32 p.m. UTC 
From: John Harrison <John.C.Harrison@Intel.com>

The above workaround was added as an engine workaround not a GT
workaround. Moved it to the correct location.

Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

Comments

Daniele Ceraolo Spurio July 24, 2020, 9:21 p.m. UTC | #1 
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>

Daniele

On 7/10/2020 2:32 PM, John.C.Harrison@Intel.com wrote:
> From: John Harrison <John.C.Harrison@Intel.com>
>
> The above workaround was added as an engine workaround not a GT
> workaround. Moved it to the correct location.
>
> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
> ---
>   drivers/gpu/drm/i915/gt/intel_workarounds.c | 10 ++++++----
>   1 file changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 5726cd0a37e0..a6548a77439c 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1191,6 +1191,12 @@ tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
>   		wa_write_or(wal,
>   			    SLICE_UNIT_LEVEL_CLKGATE,
>   			    L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
> +
> +	/* Wa_1408615072:tgl[a0] */
> +	/* Empirical testing shows this register is unaffected by engine reset. */
> +	if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
> +		wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
> +			    VSUNIT_CLKGATE_DIS_TGL);
>   }
>   
>   static void
> @@ -1648,10 +1654,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>   		wa_write_or(wal,
>   			    GEN7_SARCHKMD,
>   			    GEN7_DISABLE_SAMPLER_PREFETCH);
> -
> -		/* Wa_1408615072:tgl */
> -		wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
> -			    VSUNIT_CLKGATE_DIS_TGL);
>   	}
>   
>   	if (IS_TIGERLAKE(i915)) {
Lucas De Marchi Nov. 24, 2020, 11:07 p.m. UTC | #2 
It seems this was forgotten? We do have it for DG1, but for TGL it's not
being applied.

Lucas De Marchi

On Fri, Jul 24, 2020 at 02:21:03PM -0700, Daniele Ceraolo Spurio wrote:
>Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>
>Daniele
>
>On 7/10/2020 2:32 PM, John.C.Harrison@Intel.com wrote:
>>From: John Harrison <John.C.Harrison@Intel.com>
>>
>>The above workaround was added as an engine workaround not a GT
>>workaround. Moved it to the correct location.
>>
>>Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
>>---
>>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 10 ++++++----
>>  1 file changed, 6 insertions(+), 4 deletions(-)
>>
>>diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>index 5726cd0a37e0..a6548a77439c 100644
>>--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>@@ -1191,6 +1191,12 @@ tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
>>  		wa_write_or(wal,
>>  			    SLICE_UNIT_LEVEL_CLKGATE,
>>  			    L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
>>+
>>+	/* Wa_1408615072:tgl[a0] */
>>+	/* Empirical testing shows this register is unaffected by engine reset. */
>>+	if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
>>+		wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
>>+			    VSUNIT_CLKGATE_DIS_TGL);
>>  }
>>  static void
>>@@ -1648,10 +1654,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>>  		wa_write_or(wal,
>>  			    GEN7_SARCHKMD,
>>  			    GEN7_DISABLE_SAMPLER_PREFETCH);
>>-
>>-		/* Wa_1408615072:tgl */
>>-		wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
>>-			    VSUNIT_CLKGATE_DIS_TGL);
>>  	}
>>  	if (IS_TIGERLAKE(i915)) {
>
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>Intel-gfx@lists.freedesktop.org
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diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 5726cd0a37e0..a6548a77439c 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1191,6 +1191,12 @@  tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
 		wa_write_or(wal,
 			    SLICE_UNIT_LEVEL_CLKGATE,
 			    L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
+
+	/* Wa_1408615072:tgl[a0] */
+	/* Empirical testing shows this register is unaffected by engine reset. */
+	if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
+		wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
+			    VSUNIT_CLKGATE_DIS_TGL);
 }
 
 static void
@@ -1648,10 +1654,6 @@  rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 		wa_write_or(wal,
 			    GEN7_SARCHKMD,
 			    GEN7_DISABLE_SAMPLER_PREFETCH);
-
-		/* Wa_1408615072:tgl */
-		wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
-			    VSUNIT_CLKGATE_DIS_TGL);
 	}
 
 	if (IS_TIGERLAKE(i915)) {