set accessed bit for VMCB segment selectors
diff mbox

Message ID 12315364554190-git-send-email-andre.przywara@amd.com
State Not Applicable, archived
Headers show

Commit Message

Andre Przywara Jan. 9, 2009, 9:27 p.m. UTC
In the segment descriptor _cache_ the accessed bit is always set
(although it can be cleared in the descriptor itself). Since Intel
checks for this condition on a VMENTRY, set this bit in the AMD path
to enable cross vendor migration.

Signed-off-by: Andre Przywara <andre.przywara@amd.com>
---
 arch/x86/kvm/svm.c |   22 +++++++++++++++++++---
 1 files changed, 19 insertions(+), 3 deletions(-)

Comments

Amit Shah Jan. 10, 2009, 5:17 a.m. UTC | #1
On Fri, Jan 09, 2009 at 10:27:35PM +0100, Andre Przywara wrote:
> In the segment descriptor _cache_ the accessed bit is always set
> (although it can be cleared in the descriptor itself). Since Intel
> checks for this condition on a VMENTRY, set this bit in the AMD path
> to enable cross vendor migration.
> 
> Signed-off-by: Andre Przywara <andre.przywara@amd.com>
> ---
>  arch/x86/kvm/svm.c |   22 +++++++++++++++++++---
>  1 files changed, 19 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
> index 32dafb7..ffaba66 100644
> --- a/arch/x86/kvm/svm.c
> +++ b/arch/x86/kvm/svm.c
> @@ -793,20 +793,36 @@ static void svm_get_segment(struct kvm_vcpu *vcpu,
>  	var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
>  	var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
>  
> +	switch (seg) {
> +	case VCPU_SREG_CS:
>  	/*
>  	 * SVM always stores 0 for the 'G' bit in the CS selector in
>  	 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
>  	 * Intel's VMENTRY has a check on the 'G' bit.
>  	 */

This comment will need to be indented.

> -	if (seg == VCPU_SREG_CS)
>  		var->g = s->limit > 0xfffff;
> -
> +		break;
> +	case VCPU_SREG_TR:
>  	/*
>  	 * Work around a bug where the busy flag in the tr selector
>  	 * isn't exposed
>  	 */
> -	if (seg == VCPU_SREG_TR)
>  		var->type |= 0x2;
> +		break;
> +	case VCPU_SREG_DS:
> +	case VCPU_SREG_ES:
> +	case VCPU_SREG_FS:
> +	case VCPU_SREG_GS:
> +	/*
> +	 * The accessed bit must always be set in the segment
> +	 * descriptor cache, although it can be cleared in the
> +	 * descriptor, the cached bit always remains at 1. Since
> +	 * Intel has a check on this, set it here to support
> +	 * cross-vendor migration.
> +	 */
> +		if (!var->unusable) var->type |= 0x1;

A line break is missing after the if check.

> +		break;
> +	}
>  
>  	var->unusable = !var->present;
>  }

Other than these minor style issues,

Acked-By: Amit Shah <amit.shah@redhat.com>
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Patch
diff mbox

diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
index 32dafb7..ffaba66 100644
--- a/arch/x86/kvm/svm.c
+++ b/arch/x86/kvm/svm.c
@@ -793,20 +793,36 @@  static void svm_get_segment(struct kvm_vcpu *vcpu,
 	var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
 	var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
 
+	switch (seg) {
+	case VCPU_SREG_CS:
 	/*
 	 * SVM always stores 0 for the 'G' bit in the CS selector in
 	 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
 	 * Intel's VMENTRY has a check on the 'G' bit.
 	 */
-	if (seg == VCPU_SREG_CS)
 		var->g = s->limit > 0xfffff;
-
+		break;
+	case VCPU_SREG_TR:
 	/*
 	 * Work around a bug where the busy flag in the tr selector
 	 * isn't exposed
 	 */
-	if (seg == VCPU_SREG_TR)
 		var->type |= 0x2;
+		break;
+	case VCPU_SREG_DS:
+	case VCPU_SREG_ES:
+	case VCPU_SREG_FS:
+	case VCPU_SREG_GS:
+	/*
+	 * The accessed bit must always be set in the segment
+	 * descriptor cache, although it can be cleared in the
+	 * descriptor, the cached bit always remains at 1. Since
+	 * Intel has a check on this, set it here to support
+	 * cross-vendor migration.
+	 */
+		if (!var->unusable) var->type |= 0x1;
+		break;
+	}
 
 	var->unusable = !var->present;
 }