diff mbox

PCI: only save/restore existent registers in the PCIe capability

Message ID 1239167749-15843-1-git-send-email-yu.zhao@intel.com (mailing list archive)
State Superseded, archived
Headers show

Commit Message

Yu Zhao April 8, 2009, 5:15 a.m. UTC 
PCIe 1.1 spec neither requires the endpoint to implement the entire
PCIe capability structure nor specifies default value of registers
that are not implemented by the device. So we only save and restore
registers that must be implemented by different device types if the
device PCIe capability version is 1.

PCIe 1.1 Capability Structure Expansion ENC and PCIe 2.0 requires
all registers in the PCIe capability to be either implemented or
hardwired to 0. Their PCIe capability version is 2.

Signed-off-by: Yu Zhao <yu.zhao@intel.com>
---
 drivers/pci/pci.c        |   58 +++++++++++++++++++++++++++++++++++++++++----
 include/linux/pci_regs.h |    1 +
 2 files changed, 53 insertions(+), 6 deletions(-)

Comments

Matthew Wilcox April 8, 2009, 2:52 p.m. UTC | #1 
On Wed, Apr 08, 2009 at 01:15:49PM +0800, Yu Zhao wrote:
> PCIe 1.1 spec neither requires the endpoint to implement the entire
> PCIe capability structure nor specifies default value of registers
> that are not implemented by the device. So we only save and restore
> registers that must be implemented by different device types if the
> device PCIe capability version is 1.
> 
> PCIe 1.1 Capability Structure Expansion ENC and PCIe 2.0 requires

ECN, I think, not ENC?

> all registers in the PCIe capability to be either implemented or
> hardwired to 0. Their PCIe capability version is 2.

> +	pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
> +	cap_version = flags & PCI_EXP_FLAGS_VERS;
> +
>  	pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]);
> -	pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]);
> -	pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]);
> -	pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]);
> +
> +	if (cap_version > 1 ||
> +	    (dev->pcie_type == PCI_EXP_TYPE_ROOT_PORT ||
> +	     dev->pcie_type == PCI_EXP_TYPE_ENDPOINT ||
> +	     dev->pcie_type == PCI_EXP_TYPE_LEG_END))
> +		pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]);

It's too much effort to check that these two things are in sync between
the save and restore code.  How about doing it this way?

#define pcie_has_link_regs(dev)					\
	(dev->pcie_type == PCI_EXP_TYPE_ROOT_PORT ||		\
	 dev->pcie_type == PCI_EXP_TYPE_ENDPOINT ||		\
	 dev->pcie_type == PCI_EXP_TYPE_LEG_END)

#define pcie_has_slot_regs(dev, flags)				\
	((dev->pcie_type == PCI_EXP_TYPE_ROOT_PORT) ||		\
	 (dev->pcie_type == PCI_EXP_TYPE_DOWNSTREAM &&		\
	  (flags & PCI_EXP_FLAGS_SLOT)))

#define pcie_has_root_regs(dev)					\
	(dev->pcie_type == PCI_EXP_TYPE_ROOT_PORT ||		\
	 dev->pcie_type == PCI_EXP_TYPE_RC_EC)

...

	if (cap_version > 1 || pcie_has_link_regs(dev))
		pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]);
	if (cap_version > 1 || pcie_has_slot_regs(dev, flags))
		pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]);
	if (cap_version > 1 || pcie_has_root_regs(dev))
		pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]);

...

	if (cap_version > 1 || pcie_has_link_regs(dev))
		pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]);
	if (cap_version > 1 || pcie_has_slot_regs(dev, flags))
		pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]);
	if (cap_version > 1 || pcie_has_root_regs(dev))
		pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]);

	
>  
> +	pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
> +	cap_version = flags & PCI_EXP_FLAGS_VERS;
> +
>  	pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]);
> -	pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]);
> -	pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]);
> -	pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]);
> +
> +	if (cap_version > 1 ||
> +	    (dev->pcie_type == PCI_EXP_TYPE_ROOT_PORT ||
> +	     dev->pcie_type == PCI_EXP_TYPE_ENDPOINT ||
> +	     dev->pcie_type == PCI_EXP_TYPE_LEG_END))
> +		pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]);

You made a copy and paste error here ;-)
diff mbox

Patch

diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index fe7ac2c..635bb6b 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -686,6 +686,8 @@  static int pci_save_pcie_state(struct pci_dev *dev)
 	int pos, i = 0;
 	struct pci_cap_saved_state *save_state;
 	u16 *cap;
+	u16 flags;
+	int cap_version;
 
 	pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
 	if (pos <= 0)
@@ -698,10 +700,31 @@  static int pci_save_pcie_state(struct pci_dev *dev)
 	}
 	cap = (u16 *)&save_state->data[0];
 
+	pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
+	cap_version = flags & PCI_EXP_FLAGS_VERS;
+
 	pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]);
-	pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]);
-	pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]);
-	pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]);
+
+	if (cap_version > 1 ||
+	    (dev->pcie_type == PCI_EXP_TYPE_ROOT_PORT ||
+	     dev->pcie_type == PCI_EXP_TYPE_ENDPOINT ||
+	     dev->pcie_type == PCI_EXP_TYPE_LEG_END))
+		pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]);
+
+	if (cap_version > 1 ||
+	    ((dev->pcie_type == PCI_EXP_TYPE_ROOT_PORT) ||
+	     (dev->pcie_type == PCI_EXP_TYPE_DOWNSTREAM &&
+	      (flags & PCI_EXP_FLAGS_SLOT))))
+		pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]);
+
+	if (cap_version > 1 ||
+	    (dev->pcie_type == PCI_EXP_TYPE_ROOT_PORT ||
+	     dev->pcie_type == PCI_EXP_TYPE_RC_EC))
+		pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]);
+
+	if (cap_version == 1)
+		return 0;
+
 	pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &cap[i++]);
 	pci_read_config_word(dev, pos + PCI_EXP_LNKCTL2, &cap[i++]);
 	pci_read_config_word(dev, pos + PCI_EXP_SLTCTL2, &cap[i++]);
@@ -714,6 +737,8 @@  static void pci_restore_pcie_state(struct pci_dev *dev)
 	int i = 0, pos;
 	struct pci_cap_saved_state *save_state;
 	u16 *cap;
+	u16 flags;
+	int cap_version;
 
 	save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
 	pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
@@ -721,10 +746,31 @@  static void pci_restore_pcie_state(struct pci_dev *dev)
 		return;
 	cap = (u16 *)&save_state->data[0];
 
+	pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
+	cap_version = flags & PCI_EXP_FLAGS_VERS;
+
 	pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]);
-	pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]);
-	pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]);
-	pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]);
+
+	if (cap_version > 1 ||
+	    (dev->pcie_type == PCI_EXP_TYPE_ROOT_PORT ||
+	     dev->pcie_type == PCI_EXP_TYPE_ENDPOINT ||
+	     dev->pcie_type == PCI_EXP_TYPE_LEG_END))
+		pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]);
+
+	if (cap_version > 1 ||
+	    ((dev->pcie_type == PCI_EXP_TYPE_ROOT_PORT) ||
+	     (dev->pcie_type == PCI_EXP_TYPE_DOWNSTREAM &&
+	      (flags & PCI_EXP_FLAGS_SLOT))))
+		pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]);
+
+	if (cap_version > 1 ||
+	    (dev->pcie_type == PCI_EXP_TYPE_ROOT_PORT ||
+	     dev->pcie_type == PCI_EXP_TYPE_RC_EC))
+		pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]);
+
+	if (cap_version == 1)
+		return;
+
 	pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, cap[i++]);
 	pci_write_config_word(dev, pos + PCI_EXP_LNKCTL2, cap[i++]);
 	pci_write_config_word(dev, pos + PCI_EXP_SLTCTL2, cap[i++]);
diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h
index e4d08c1..616bf8b 100644
--- a/include/linux/pci_regs.h
+++ b/include/linux/pci_regs.h
@@ -376,6 +376,7 @@ 
 #define  PCI_EXP_TYPE_DOWNSTREAM 0x6	/* Downstream Port */
 #define  PCI_EXP_TYPE_PCI_BRIDGE 0x7	/* PCI/PCI-X Bridge */
 #define  PCI_EXP_TYPE_RC_END	0x9	/* Root Complex Integrated Endpoint */
+#define  PCI_EXP_TYPE_RC_EC	0x10	/* Root Complex Event Collector */
 #define PCI_EXP_FLAGS_SLOT	0x0100	/* Slot implemented */
 #define PCI_EXP_FLAGS_IRQ	0x3e00	/* Interrupt message number */
 #define PCI_EXP_DEVCAP		4	/* Device capabilities */