| Message ID | 1242375740-31222-3-git-send-email-agraf@suse.de (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Fri, May 15, 2009 at 10:22:16AM +0200, Alexander Graf wrote: > A 64bit PTE can have bit7 set to 1 which means "Use this bit for the PAT". > Currently KVM's MMU code treats this bit as reserved, even though it's not. > > As long as we're not required to make use of the PAT bits which is only > required for DMA/MMIO from my understanding, we can safely ignore it. > > Hyper-V uses this bit for kernel PTEs. > > Signed-off-by: Alexander Graf <agraf@suse.de> > --- > arch/x86/kvm/mmu.c | 2 +- > 1 files changed, 1 insertions(+), 1 deletions(-) > > diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c > index 8fcdae9..cce055a 100644 > --- a/arch/x86/kvm/mmu.c > +++ b/arch/x86/kvm/mmu.c > @@ -2169,7 +2169,7 @@ static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, int level) > context->rsvd_bits_mask[1][1] = exb_bit_rsvd | > rsvd_bits(maxphyaddr, 51) | > rsvd_bits(13, 20); /* large page */ > - context->rsvd_bits_mask[1][0] = ~0ull; > + context->rsvd_bits_mask[1][0] = 0ull; > break; > } > } Just to make sure I understand what this does: if guest sets bit7, will bit7 get set in shadow PTEs as well?
On 15.05.2009, at 12:25, Michael S. Tsirkin wrote: > On Fri, May 15, 2009 at 10:22:16AM +0200, Alexander Graf wrote: >> A 64bit PTE can have bit7 set to 1 which means "Use this bit for >> the PAT". >> Currently KVM's MMU code treats this bit as reserved, even though >> it's not. >> >> As long as we're not required to make use of the PAT bits which is >> only >> required for DMA/MMIO from my understanding, we can safely ignore it. >> >> Hyper-V uses this bit for kernel PTEs. >> >> Signed-off-by: Alexander Graf <agraf@suse.de> >> --- >> arch/x86/kvm/mmu.c | 2 +- >> 1 files changed, 1 insertions(+), 1 deletions(-) >> >> diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c >> index 8fcdae9..cce055a 100644 >> --- a/arch/x86/kvm/mmu.c >> +++ b/arch/x86/kvm/mmu.c >> @@ -2169,7 +2169,7 @@ static void reset_rsvds_bits_mask(struct >> kvm_vcpu *vcpu, int level) >> context->rsvd_bits_mask[1][1] = exb_bit_rsvd | >> rsvd_bits(maxphyaddr, 51) | >> rsvd_bits(13, 20); /* large page */ >> - context->rsvd_bits_mask[1][0] = ~0ull; >> + context->rsvd_bits_mask[1][0] = 0ull; >> break; >> } >> } > > Just to make sure I understand what this does: if guest sets bit7, > will > bit7 get set in shadow PTEs as well? I don't see any code that interprets bit7, so the shadow PTE should be completely unaffected. But to be sure I asked Jörg to take a look at it as well, as he's more familiar with the x86 SPT code than I am :-). Alex -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c index 8fcdae9..cce055a 100644 --- a/arch/x86/kvm/mmu.c +++ b/arch/x86/kvm/mmu.c @@ -2169,7 +2169,7 @@ static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, int level) context->rsvd_bits_mask[1][1] = exb_bit_rsvd | rsvd_bits(maxphyaddr, 51) | rsvd_bits(13, 20); /* large page */ - context->rsvd_bits_mask[1][0] = ~0ull; + context->rsvd_bits_mask[1][0] = 0ull; break; } }
A 64bit PTE can have bit7 set to 1 which means "Use this bit for the PAT". Currently KVM's MMU code treats this bit as reserved, even though it's not. As long as we're not required to make use of the PAT bits which is only required for DMA/MMIO from my understanding, we can safely ignore it. Hyper-V uses this bit for kernel PTEs. Signed-off-by: Alexander Graf <agraf@suse.de> --- arch/x86/kvm/mmu.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)