Message ID | 1437382798-16061-1-git-send-email-prladdha@cisco.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
diff --git a/utils/v4l2-ctl/v4l2-ctl-modes.cpp b/utils/v4l2-ctl/v4l2-ctl-modes.cpp index e44b229..236f19f 100644 --- a/utils/v4l2-ctl/v4l2-ctl-modes.cpp +++ b/utils/v4l2-ctl/v4l2-ctl-modes.cpp @@ -336,7 +336,7 @@ bool calc_cvt_modeline(int image_width, int image_height, } else { cvt->polarities = V4L2_DV_VSYNC_POS_POL; } - if (reduced_fps && v_refresh % 6 == 0) + if (rb_v2 && reduced_fps && v_refresh % 6 == 0) cvt->flags |= V4L2_DV_FL_REDUCED_FPS; return true;
In the absence of reduced blanking v2, the clock granularity is not sufficient enough to allow pixel clock reduction done by factor of 1000 / 1001 in case of reduced fps. Cc: Hans Verkuil <hans.verkuil@cisco.com> Signed-off-by: Prashant Laddha <prladdha@cisco.com> --- utils/v4l2-ctl/v4l2-ctl-modes.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)