diff mbox

[4/4] drm/i915: Do not allocate unused PPAT entries

Message ID 1504208177-27784-4-git-send-email-zhi.a.wang@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Wang, Zhi A Aug. 31, 2017, 7:36 p.m. UTC 
Only PPAT entries 0/2/3/4 are using. Remove extra PPAT entry allocation
during initialization.

Cc: Ben Widawsky <benjamin.widawsky@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Suggested-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 46 ++++++++++++++++---------------------
 drivers/gpu/drm/i915/i915_gem_gtt.h |  7 ++++++
 2 files changed, 27 insertions(+), 26 deletions(-)
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 51bb382..57f719d 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2988,18 +2988,15 @@  static void cnl_setup_private_ppat(struct intel_ppat *ppat)
 
 	/* XXX: spec is unclear if this is still needed for CNL+ */
 	if (!USES_PPGTT(ppat->i915)) {
-		__alloc_ppat_entry(ppat, 0, GEN8_PPAT_UC);
+		__alloc_ppat_entry(ppat, ppat_bits_to_index(PPAT_CACHED_PDE_INDEX), GEN8_PPAT_UC);
 		return;
 	}
 
-	__alloc_ppat_entry(ppat, 0, GEN8_PPAT_WB | GEN8_PPAT_LLC);
-	__alloc_ppat_entry(ppat, 1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC);
-	__alloc_ppat_entry(ppat, 2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC);
-	__alloc_ppat_entry(ppat, 3, GEN8_PPAT_UC);
-	__alloc_ppat_entry(ppat, 4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0));
-	__alloc_ppat_entry(ppat, 5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1));
-	__alloc_ppat_entry(ppat, 6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2));
-	__alloc_ppat_entry(ppat, 7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
+	/* See gen8_pte_encode() for the mapping from cache-level to PPAT */
+	__alloc_ppat_entry(ppat, ppat_bits_to_index(PPAT_CACHED_PDE_INDEX), GEN8_PPAT_WB | GEN8_PPAT_LLC);
+	__alloc_ppat_entry(ppat, ppat_bits_to_index(PPAT_DISPLAY_ELLC_INDEX), GEN8_PPAT_WT | GEN8_PPAT_LLCELLC);
+	__alloc_ppat_entry(ppat, ppat_bits_to_index(PPAT_UNCACHED_INDEX), GEN8_PPAT_UC);
+	__alloc_ppat_entry(ppat, ppat_bits_to_index(PPAT_CACHED_INDEX), GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0));
 }
 
 /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
@@ -3026,18 +3023,18 @@  static void bdw_setup_private_ppat(struct intel_ppat *ppat)
 		 * So we can still hold onto all our assumptions wrt cpu
 		 * clflushing on LLC machines.
 		 */
-		__alloc_ppat_entry(ppat, 0, GEN8_PPAT_UC);
+		__alloc_ppat_entry(ppat, ppat_bits_to_index(PPAT_CACHED_PDE_INDEX), GEN8_PPAT_UC);
 		return;
 	}
 
-	__alloc_ppat_entry(ppat, 0, GEN8_PPAT_WB | GEN8_PPAT_LLC);      /* for normal objects, no eLLC */
-	__alloc_ppat_entry(ppat, 1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC);  /* for something pointing to ptes? */
-	__alloc_ppat_entry(ppat, 2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC);  /* for scanout with eLLC */
-	__alloc_ppat_entry(ppat, 3, GEN8_PPAT_UC);                      /* Uncached objects, mostly for scanout */
-	__alloc_ppat_entry(ppat, 4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0));
-	__alloc_ppat_entry(ppat, 5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1));
-	__alloc_ppat_entry(ppat, 6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2));
-	__alloc_ppat_entry(ppat, 7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
+	/* See gen8_pte_encode() for the mapping from cache-level to PPAT */
+	/* for normal objects, no eLLC */
+	__alloc_ppat_entry(ppat, ppat_bits_to_index(PPAT_CACHED_PDE_INDEX), GEN8_PPAT_WB | GEN8_PPAT_LLC);
+	/* for scanout with eLLC */
+	__alloc_ppat_entry(ppat, ppat_bits_to_index(PPAT_DISPLAY_ELLC_INDEX), GEN8_PPAT_WT | GEN8_PPAT_LLCELLC);
+	/* Uncached objects, mostly for scanout */
+	__alloc_ppat_entry(ppat, ppat_bits_to_index(PPAT_UNCACHED_INDEX), GEN8_PPAT_UC);
+	__alloc_ppat_entry(ppat, ppat_bits_to_index(PPAT_CACHED_INDEX), GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0));
 }
 
 static void chv_setup_private_ppat(struct intel_ppat *ppat)
@@ -3066,14 +3063,11 @@  static void chv_setup_private_ppat(struct intel_ppat *ppat)
 	 * in order to keep the global status page working.
 	 */
 
-	__alloc_ppat_entry(ppat, 0, CHV_PPAT_SNOOP);
-	__alloc_ppat_entry(ppat, 1, 0);
-	__alloc_ppat_entry(ppat, 2, 0);
-	__alloc_ppat_entry(ppat, 3, 0);
-	__alloc_ppat_entry(ppat, 4, CHV_PPAT_SNOOP);
-	__alloc_ppat_entry(ppat, 5, CHV_PPAT_SNOOP);
-	__alloc_ppat_entry(ppat, 6, CHV_PPAT_SNOOP);
-	__alloc_ppat_entry(ppat, 7, CHV_PPAT_SNOOP);
+	/* See gen8_pte_encode() for the mapping from cache-level to PPAT */
+	__alloc_ppat_entry(ppat, ppat_bits_to_index(PPAT_CACHED_PDE_INDEX), CHV_PPAT_SNOOP);
+	__alloc_ppat_entry(ppat, ppat_bits_to_index(PPAT_DISPLAY_ELLC_INDEX), 0);
+	__alloc_ppat_entry(ppat, ppat_bits_to_index(PPAT_UNCACHED_INDEX), 0);
+	__alloc_ppat_entry(ppat, ppat_bits_to_index(PPAT_CACHED_INDEX), CHV_PPAT_SNOOP);
 }
 
 static void gen6_gmch_remove(struct i915_address_space *vm)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
index e10ca89..575da15 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -131,6 +131,13 @@  typedef u64 gen8_ppgtt_pml4e_t;
 #define PPAT_CACHED_INDEX		_PAGE_PAT /* WB LLCeLLC */
 #define PPAT_DISPLAY_ELLC_INDEX		_PAGE_PCD /* WT eLLC */
 
+/* PPAT index = 4 * PAT + 2 * PCD + PWT */
+static inline unsigned int ppat_bits_to_index(unsigned int bits)
+{
+	return (4 * !!(bits & _PAGE_PAT) + 2 * !!(bits & _PAGE_PCD)
+		+ !!(bits & _PAGE_PWT));
+}
+
 #define CHV_PPAT_SNOOP			(1<<6)
 #define GEN8_PPAT_AGE(x)		(x<<4)
 #define GEN8_PPAT_LLCeLLC		(3<<2)