[5.10.y-cip,02/24] serial: sh-sci: Add support for RZ/G2L SoC

From: Biju Das <biju.das.jz@bp.renesas.com>

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
To: cip-dev@lists.cip-project.org,
	Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>,
	Pavel Machek <pavel@denx.de>
Cc: Biju Das <biju.das.jz@bp.renesas.com>
Subject: [PATCH 5.10.y-cip 02/24] serial: sh-sci: Add support for RZ/G2L SoC
Date: Thu, 16 Dec 2021 12:54:24 +0000
Message-Id: <20211216125446.15451-3-prabhakar.mahadev-lad.rj@bp.renesas.com>
In-Reply-To: <20211216125446.15451-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
References: <20211216125446.15451-1-prabhakar.mahadev-lad.rj@bp.renesas.com>

Message ID	20211216125446.15451-3-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive)
State	Accepted
Delegated to:	Pavel Machek
Headers	show Return-Path: <prabhakar.mahadev-lad.rj@bp.renesas.com> ip: 210.160.252.172, mailfrom: prabhakar.mahadev-lad.rj@bp.renesas.com) From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>, Pavel Machek <pavel@denx.de> Cc: Biju Das <biju.das.jz@bp.renesas.com> Subject: [PATCH 5.10.y-cip 02/24] serial: sh-sci: Add support for RZ/G2L SoC Date: Thu, 16 Dec 2021 12:54:24 +0000 Message-Id: <20211216125446.15451-3-prabhakar.mahadev-lad.rj@bp.renesas.com> In-Reply-To: <20211216125446.15451-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20211216125446.15451-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
Series	Add CPG and initial DTS/I for Renesas RZ/G2L SoC + SMARC EVK \| expand [5.10.y-cip,00/24] Add CPG and initial DTS/I for Renesas RZ/G2L SoC + SMARC EVK [5.10.y-cip,01/24] dt-bindings: serial: renesas,scif: Document r9a07g044 bindings [5.10.y-cip,02/24] serial: sh-sci: Add support for RZ/G2L SoC [5.10.y-cip,03/24] dt-bindings: clock: renesas: Document RZ/G2L SoC CPG driver [5.10.y-cip,04/24] dt-bindings: clock: Add r9a07g044 CPG Clock Definitions [5.10.y-cip,05/24] clk: renesas: Add CPG core wrapper for RZ/G2L SoC [5.10.y-cip,06/24] clk: renesas: Add support for R9A07G044 SoC [5.10.y-cip,07/24] clk: renesas: r9a07g044: Rename divider table [5.10.y-cip,08/24] clk: renesas: r9a07g044: Fix P1 Clock [5.10.y-cip,09/24] clk: renesas: r9a07g044: Add P2 Clock support [5.10.y-cip,10/24] clk: renesas: rzg2l: Add multi clock PM support [5.10.y-cip,11/24] arm64: dts: renesas: Add initial DTSI for RZ/G2{L,LC} SoC's [5.10.y-cip,12/24] arm64: dts: renesas: Add initial device tree for RZ/G2L SMARC EVK [5.10.y-cip,13/24] arm64: dts: renesas: r9a07g044: Add SYSC node [5.10.y-cip,14/24] dt-bindings: clock: r9a07g044-cpg: Update clock/reset definitions [5.10.y-cip,15/24] clk: renesas: rzg2l: Remove unneeded semicolon [5.10.y-cip,16/24] clk: renesas: rzg2l: Fix return value and unused assignment [5.10.y-cip,17/24] clk: renesas: rzg2l: Fix a double free on error [5.10.y-cip,18/24] clk: renesas: rzg2l: Avoid mixing error pointers and NULL [5.10.y-cip,19/24] clk: renesas: rzg2l: Fix off-by-one check in rzg2l_cpg_clk_src_twocell_get() [5.10.y-cip,20/24] clk: renesas: Rename renesas-rzg2l-cpg.[ch] to rzg2l-cpg.[ch] [5.10.y-cip,21/24] clk: mux: provide devm_clk_hw_register_mux() [5.10.y-cip,22/24] clk: renesas: rzg2l: Add support to handle MUX clocks [5.10.y-cip,23/24] clk: renesas: rzg2l: Add support to handle coupled clocks [5.10.y-cip,24/24] clk: renesas: rzg2l: Fix clk status function

[5.10.y-cip,02/24] serial: sh-sci: Add support for RZ/G2L SoC

Commit Message

Patch