diff mbox series

[5.10.y-cip,11/13] arm64: dts: renesas: rzg2l-smarc: Add support for enabling MTU3

Message ID 20230718140608.119449-12-biju.das.jz@bp.renesas.com (mailing list archive)
State Superseded
Headers show
Series Add RZ/{G2L,G2LC,V2L} MTU3 support. | expand

Commit Message

Biju Das July 18, 2023, 2:06 p.m. UTC
commit fb9341ebc7df140813d4fbc4a29fddba55a90728 upstream.

Add support for PMOD_MTU3 macro to enable MTU3 node on RZ/{G2,V2}L SMARC
EVK.

The MTU3a PWM pins are muxed with spi1 pins and counter external input
phase clock pins are muxed with scif2 pins. Disable these IPs when
PMOD_MTU3 macro is enabled.

Apart from this, the counter Z phase clock signal is muxed with the
SDHI1 cd signal. So disable SDHI1 IP, when the counter Z phase signal
is enabled.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230706153047.368993-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 .../boot/dts/renesas/r9a07g044l2-smarc.dts    | 21 +++++++++++++++++
 .../boot/dts/renesas/r9a07g054l2-smarc.dts    | 20 ++++++++++++++++
 .../dts/renesas/rzg2l-smarc-pinfunction.dtsi  | 20 ++++++++++++++++
 arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi  | 23 ++++++++++++++++---
 4 files changed, 81 insertions(+), 3 deletions(-)

Comments

Pavel Machek July 19, 2023, 12:39 p.m. UTC | #1
Hi!

> commit fb9341ebc7df140813d4fbc4a29fddba55a90728 upstream.
> 
> Add support for PMOD_MTU3 macro to enable MTU3 node on RZ/{G2,V2}L SMARC
> EVK.
> 
> The MTU3a PWM pins are muxed with spi1 pins and counter external input
> phase clock pins are muxed with scif2 pins. Disable these IPs when
> PMOD_MTU3 macro is enabled.
> 
> Apart from this, the counter Z phase clock signal is muxed with the
> SDHI1 cd signal. So disable SDHI1 IP, when the counter Z phase signal
> is enabled.

> +++ b/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts
> @@ -6,6 +6,27 @@
> +
> +#if (PMOD_MTU3 && PMOD1_SER0)
> +#error "Cannot set as PMOD_MTU3 and PMOD1_SER0 are mutually exclusive "
> +#endif
> +
> +#define MTU3_COUNTER_Z_PHASE_SIGNAL	0
> +
> +#if (!PMOD_MTU3 && MTU3_COUNTER_Z_PHASE_SIGNAL)
> +#error "Cannot set 1 to MTU3_COUNTER_Z_PHASE_SIGNAL as PMOD_MTU3=0"
> +#endif
> +
>  #include "r9a07g044l2.dtsi"
>  #include "rzg2l-smarc-som.dtsi"
>  #include "rzg2l-smarc-pinfunction.dtsi"
> diff --git a/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts
> index 3d01a4cf0fbe..b3e6016880dd 100644
> --- a/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts
> +++ b/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts
> @@ -6,6 +6,26 @@
> +
> +#if (PMOD_MTU3 && PMOD1_SER0)
> +#error "Cannot set as PMOD_MTU3 and PMOD1_SER0 are mutually exclusive "
> +#endif
> +
> +#define MTU3_COUNTER_Z_PHASE_SIGNAL	0
> +#if (!PMOD_MTU3 && MTU3_COUNTER_Z_PHASE_SIGNAL)
> +#error "Cannot set 1 to MTU3_COUNTER_Z_PHASE_SIGNAL as PMOD_MTU3=0"
> +#endif
> +

These consistency checks are common, could they be done in a common
place?

Best regards,
								Pavel
Biju Das July 19, 2023, 1:06 p.m. UTC | #2
Hi Pavel,

Thanks for the feedback.

> Subject: Re: [PATCH 5.10.y-cip 11/13] arm64: dts: renesas: rzg2l-smarc:
> Add support for enabling MTU3
> 
> Hi!
> 
> > commit fb9341ebc7df140813d4fbc4a29fddba55a90728 upstream.
> >
> > Add support for PMOD_MTU3 macro to enable MTU3 node on RZ/{G2,V2}L
> > SMARC EVK.
> >
> > The MTU3a PWM pins are muxed with spi1 pins and counter external input
> > phase clock pins are muxed with scif2 pins. Disable these IPs when
> > PMOD_MTU3 macro is enabled.
> >
> > Apart from this, the counter Z phase clock signal is muxed with the
> > SDHI1 cd signal. So disable SDHI1 IP, when the counter Z phase signal
> > is enabled.
> 
> > +++ b/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts
> > @@ -6,6 +6,27 @@
> > +
> > +#if (PMOD_MTU3 && PMOD1_SER0)
> > +#error "Cannot set as PMOD_MTU3 and PMOD1_SER0 are mutually exclusive
> "
> > +#endif
> > +
> > +#define MTU3_COUNTER_Z_PHASE_SIGNAL	0
> > +
> > +#if (!PMOD_MTU3 && MTU3_COUNTER_Z_PHASE_SIGNAL) #error "Cannot set 1
> > +to MTU3_COUNTER_Z_PHASE_SIGNAL as PMOD_MTU3=0"
> > +#endif
> > +
> >  #include "r9a07g044l2.dtsi"
> >  #include "rzg2l-smarc-som.dtsi"
> >  #include "rzg2l-smarc-pinfunction.dtsi"
> > diff --git a/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts
> > b/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts
> > index 3d01a4cf0fbe..b3e6016880dd 100644
> > --- a/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts
> > +++ b/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts
> > @@ -6,6 +6,26 @@
> > +
> > +#if (PMOD_MTU3 && PMOD1_SER0)
> > +#error "Cannot set as PMOD_MTU3 and PMOD1_SER0 are mutually exclusive
> "
> > +#endif
> > +
> > +#define MTU3_COUNTER_Z_PHASE_SIGNAL	0
> > +#if (!PMOD_MTU3 && MTU3_COUNTER_Z_PHASE_SIGNAL) #error "Cannot set 1
> > +to MTU3_COUNTER_Z_PHASE_SIGNAL as PMOD_MTU3=0"
> > +#endif
> > +
> 
> These consistency checks are common, could they be done in a common
> place?

Yes, you are right. It should be in common place to avoid code duplication.

Cheers,
Biju
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts
index bc2af6c92ccd..568d49cfe44a 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts
+++ b/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts
@@ -6,6 +6,27 @@ 
  */
 
 /dts-v1/;
+
+/* Enable SCIF2 (SER0) on PMOD1 (CN7) */
+#define PMOD1_SER0	1
+
+/*
+ * To enable MTU3a PWM on PMOD0,
+ * Disable PMOD1_SER0 by setting "#define PMOD1_SER0	0" above and
+ * enable PMOD_MTU3 by setting "#define PMOD_MTU3	1" below.
+ */
+#define PMOD_MTU3	0
+
+#if (PMOD_MTU3 && PMOD1_SER0)
+#error "Cannot set as PMOD_MTU3 and PMOD1_SER0 are mutually exclusive "
+#endif
+
+#define MTU3_COUNTER_Z_PHASE_SIGNAL	0
+
+#if (!PMOD_MTU3 && MTU3_COUNTER_Z_PHASE_SIGNAL)
+#error "Cannot set 1 to MTU3_COUNTER_Z_PHASE_SIGNAL as PMOD_MTU3=0"
+#endif
+
 #include "r9a07g044l2.dtsi"
 #include "rzg2l-smarc-som.dtsi"
 #include "rzg2l-smarc-pinfunction.dtsi"
diff --git a/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts
index 3d01a4cf0fbe..b3e6016880dd 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts
+++ b/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts
@@ -6,6 +6,26 @@ 
  */
 
 /dts-v1/;
+
+/* Enable SCIF2 (SER0) on PMOD1 (CN7) */
+#define PMOD1_SER0	1
+
+/*
+ * To enable MTU3a PWM on PMOD0,
+ * Disable PMOD1_SER0 by setting "#define PMOD1_SER0	0" above and
+ * enable PMOD_MTU3 by setting "#define PMOD_MTU3	1" below.
+ */
+#define PMOD_MTU3	0
+
+#if (PMOD_MTU3 && PMOD1_SER0)
+#error "Cannot set as PMOD_MTU3 and PMOD1_SER0 are mutually exclusive "
+#endif
+
+#define MTU3_COUNTER_Z_PHASE_SIGNAL	0
+#if (!PMOD_MTU3 && MTU3_COUNTER_Z_PHASE_SIGNAL)
+#error "Cannot set 1 to MTU3_COUNTER_Z_PHASE_SIGNAL as PMOD_MTU3=0"
+#endif
+
 #include "r9a07g054l2.dtsi"
 #include "rzg2l-smarc-som.dtsi"
 #include "rzg2l-smarc-pinfunction.dtsi"
diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi
index 9085d8c76ce1..18c526c7a4cf 100644
--- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi
@@ -53,6 +53,26 @@  i2c3_pins: i2c3 {
 			 <RZG2L_PORT_PINMUX(18, 1, 3)>; /* SCL */
 	};
 
+	mtu3_pins: mtu3 {
+		mtu3-ext-clk-input-pin {
+			pinmux = <RZG2L_PORT_PINMUX(48, 0, 4)>, /* MTCLKA */
+				 <RZG2L_PORT_PINMUX(48, 1, 4)>; /* MTCLKB */
+		};
+
+		mtu3-pwm {
+			pinmux = <RZG2L_PORT_PINMUX(44, 0, 4)>, /* MTIOC3A */
+				 <RZG2L_PORT_PINMUX(44, 1, 4)>, /* MTIOC3B */
+				 <RZG2L_PORT_PINMUX(44, 2, 4)>, /* MTIOC3C */
+				 <RZG2L_PORT_PINMUX(44, 3, 4)>; /* MTIOC3D */
+		};
+
+#if MTU3_COUNTER_Z_PHASE_SIGNAL
+		mtu3-zphase-clk {
+			pinmux = <RZG2L_PORT_PINMUX(19, 0, 3)>; /* MTIOC1A */
+		};
+#endif /* MTU3_COUNTER_Z_PHASE_SIGNAL */
+	};
+
 	scif0_pins: scif0 {
 		pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>,	/* TxD */
 			 <RZG2L_PORT_PINMUX(38, 1, 1)>;	/* RxD */
diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
index e180a955b6ac..018c34f841bf 100644
--- a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
@@ -8,9 +8,6 @@ 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
 
-/* comment the #define statement to disable SCIF2 (SER0) on PMOD1 (CN7) */
-#define PMOD1_SER0	1
-
 / {
 	aliases {
 		serial1 = &scif2;
@@ -36,6 +33,26 @@  wm8978: codec@1a {
 	};
 };
 
+#if PMOD_MTU3
+&mtu3 {
+	pinctrl-0 = <&mtu3_pins>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+#if MTU3_COUNTER_Z_PHASE_SIGNAL
+/* SDHI cd pin is muxed with counter Z phase signal */
+&sdhi1 {
+	status = "disabled";
+};
+#endif /* MTU3_COUNTER_Z_PHASE_SIGNAL */
+
+&spi1 {
+	status = "disabled";
+};
+#endif /* PMOD_MTU3 */
+
 /*
  * To enable SCIF2 (SER0) on PMOD1 (CN7)
  * SW1 should be at position 2->3 so that SER0_CTS# line is activated