| Message ID | 20230905160737.167877-17-biju.das.jz@bp.renesas.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Add Renesas RZ/G2L DSI,VSP,FCP support | expand |
Hi, > -----Original Message----- > From: Biju Das <biju.das.jz@bp.renesas.com> > Sent: Wednesday, September 6, 2023 1:08 AM > To: cip-dev@lists.cip-project.org; iwamatsu nobuhiro(岩松 信洋 ○ＤＩＴＣ□ > ＤＩＴ○ＯＳＴ) <nobuhiro1.iwamatsu@toshiba.co.jp>; Pavel Machek > <pavel@denx.de> > Cc: Biju Das <biju.das.jz@bp.renesas.com>; Lad Prabhakar > <prabhakar.mahadev-lad.rj@bp.renesas.com> > Subject: [PATCH 6.1.y-cip 16/20] arm64: dts: renesas: r9a07g044: Add DU node > > Add DU node to RZ/G2L SoC DTSI. > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> You forgot to add the original commit ID and Signed-off. Best regards, Nobuhiro > --- > arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) > > diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi > b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi > index 52279d3222a0..2eba9e8e5ae7 100644 > --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi > +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi > @@ -741,6 +741,20 @@ fcpvd: fcp@10880000 { > resets = <&cpg R9A07G044_LCDC_RESET_N>; > }; > > + du: display@10890000 { > + compatible = "renesas,r9a07g044-du"; > + reg = <0 0x10890000 0 0x10000>; > + interrupts = <GIC_SPI 152 > IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&cpg CPG_MOD > R9A07G044_LCDC_CLK_A>, > + <&cpg CPG_MOD > R9A07G044_LCDC_CLK_P>, > + <&cpg CPG_MOD > R9A07G044_LCDC_CLK_D>; > + clock-names = "aclk", "pclk", "vclk"; > + power-domains = <&cpg>; > + resets = <&cpg R9A07G044_LCDC_RESET_N>; > + renesas,vsps = <&vspd 0>; > + status = "disabled"; > + }; > + > cpg: clock-controller@11010000 { > compatible = "renesas,r9a07g044-cpg"; > reg = <0 0x11010000 0 0x10000>; > -- > 2.25.1
Hi Nobuhiro-San, > Subject: RE: [PATCH 6.1.y-cip 16/20] arm64: dts: renesas: r9a07g044: Add DU > node > > Hi, > > > -----Original Message----- > > From: Biju Das <biju.das.jz@bp.renesas.com> > > Sent: Wednesday, September 6, 2023 1:08 AM > > To: cip-dev@lists.cip-project.org; iwamatsu nobuhiro(岩松 信洋 ○ＤＩＴＣ□ > > ＤＩＴ○ＯＳＴ) <nobuhiro1.iwamatsu@toshiba.co.jp>; Pavel Machek > > <pavel@denx.de> > > Cc: Biju Das <biju.das.jz@bp.renesas.com>; Lad Prabhakar > > <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Subject: [PATCH 6.1.y-cip 16/20] arm64: dts: renesas: r9a07g044: Add > > DU node > > > > Add DU node to RZ/G2L SoC DTSI. > > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > > You forgot to add the original commit ID and Signed-off. This patch is still in review state[1]. I have added here for testing purpose as mentioned in the covering letter. [1] https://patchwork.kernel.org/project/linux-renesas-soc/list/?series=742810 Cheers, Biju > > > > --- > > arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 14 ++++++++++++++ > > 1 file changed, 14 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi > > b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi > > index 52279d3222a0..2eba9e8e5ae7 100644 > > --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi > > +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi > > @@ -741,6 +741,20 @@ fcpvd: fcp@10880000 { > > resets = <&cpg R9A07G044_LCDC_RESET_N>; > > }; > > > > + du: display@10890000 { > > + compatible = "renesas,r9a07g044-du"; > > + reg = <0 0x10890000 0 0x10000>; > > + interrupts = <GIC_SPI 152 > > IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&cpg CPG_MOD > > R9A07G044_LCDC_CLK_A>, > > + <&cpg CPG_MOD > > R9A07G044_LCDC_CLK_P>, > > + <&cpg CPG_MOD > > R9A07G044_LCDC_CLK_D>; > > + clock-names = "aclk", "pclk", "vclk"; > > + power-domains = <&cpg>; > > + resets = <&cpg R9A07G044_LCDC_RESET_N>; > > + renesas,vsps = <&vspd 0>; > > + status = "disabled"; > > + }; > > + > > cpg: clock-controller@11010000 { > > compatible = "renesas,r9a07g044-cpg"; > > reg = <0 0x11010000 0 0x10000>; > > -- > > 2.25.1
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index 52279d3222a0..2eba9e8e5ae7 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -741,6 +741,20 @@ fcpvd: fcp@10880000 { resets = <&cpg R9A07G044_LCDC_RESET_N>; }; + du: display@10890000 { + compatible = "renesas,r9a07g044-du"; + reg = <0 0x10890000 0 0x10000>; + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A07G044_LCDC_CLK_A>, + <&cpg CPG_MOD R9A07G044_LCDC_CLK_P>, + <&cpg CPG_MOD R9A07G044_LCDC_CLK_D>; + clock-names = "aclk", "pclk", "vclk"; + power-domains = <&cpg>; + resets = <&cpg R9A07G044_LCDC_RESET_N>; + renesas,vsps = <&vspd 0>; + status = "disabled"; + }; + cpg: clock-controller@11010000 { compatible = "renesas,r9a07g044-cpg"; reg = <0 0x11010000 0 0x10000>;