@@ -13,14 +13,13 @@ menuconfig CXL_BUS
if CXL_BUS
-config CXL_MEM
- tristate "CXL.mem: Memory Devices"
+config CXL_PCI
+ tristate "PCI manageability"
default CXL_BUS
help
- The CXL.mem protocol allows a device to act as a provider of
- "System RAM" and/or "Persistent Memory" that is fully coherent
- as if the memory was attached to the typical CPU memory
- controller.
+ The CXL specification defines a set of interfaces which are controlled
+ through well known PCI configuration mechanisms. Such access is
+ referred to CXL.io in the specification.
Say 'y/m' to enable a driver that will attach to CXL.mem devices for
configuration and management primarily via the mailbox interface. See
@@ -31,7 +30,7 @@ config CXL_MEM
config CXL_MEM_RAW_COMMANDS
bool "RAW Command Interface for Memory Devices"
- depends on CXL_MEM
+ depends on CXL_PCI
help
Enable CXL RAW command interface.
@@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_CXL_BUS) += core/
-obj-$(CONFIG_CXL_MEM) += cxl_pci.o
+obj-$(CONFIG_CXL_PCI) += cxl_pci.o
obj-$(CONFIG_CXL_ACPI) += cxl_acpi.o
obj-$(CONFIG_CXL_PMEM) += cxl_pmem.o
With the upcoming introduction of a driver to control the non-PCI aspects of CXL.mem, such as interleave set creation and configuration, there will be an opportunity to disconnection control over CXL device memory and CXL device manageability. CXL device manageability is implemented by the cxl_pci driver. Doing this rename allows the CXL memory driver to be enabled by a new config option independently of CXL device manageability through CXL.io/PCI mechanisms. Suggested-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Ben Widawsky <ben.widawsky@intel.com> --- drivers/cxl/Kconfig | 13 ++++++------- drivers/cxl/Makefile | 2 +- 2 files changed, 7 insertions(+), 8 deletions(-)