diff mbox

[5/5] drm/radeon: Use VRAM for indirect buffers on >= SI

Message ID 1405591275-14461-6-git-send-email-michel@daenzer.net (mailing list archive)
State New, archived
Headers show

Commit Message

Michel Dänzer July 17, 2014, 10:01 a.m. UTC 
From: Michel Dänzer <michel.daenzer@amd.com>

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
---
 drivers/gpu/drm/radeon/cik.c         | 3 +++
 drivers/gpu/drm/radeon/cik_sdma.c    | 2 ++
 drivers/gpu/drm/radeon/ni.c          | 3 +++
 drivers/gpu/drm/radeon/ni_dma.c      | 2 ++
 drivers/gpu/drm/radeon/radeon_ring.c | 2 +-
 5 files changed, 11 insertions(+), 1 deletion(-)
diff mbox

Patch

diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index df39095..8af5c9a 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -3846,6 +3846,9 @@  void cik_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
 			  (ib->gpu_addr & 0xFFFFFFFC));
 	radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
 	radeon_ring_write(ring, control);
+
+	/* Flush HDP cache */
+	WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0);
 }
 
 /**
diff --git a/drivers/gpu/drm/radeon/cik_sdma.c b/drivers/gpu/drm/radeon/cik_sdma.c
index 3396b28..2ab873d 100644
--- a/drivers/gpu/drm/radeon/cik_sdma.c
+++ b/drivers/gpu/drm/radeon/cik_sdma.c
@@ -158,6 +158,8 @@  void cik_sdma_ring_ib_execute(struct radeon_device *rdev,
 	radeon_ring_write(ring, upper_32_bits(ib->gpu_addr));
 	radeon_ring_write(ring, ib->length_dw);
 
+	/* Flush HDP cache */
+	WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0);
 }
 
 /**
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index b589fe7..ea58e5b 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -1397,6 +1397,9 @@  void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
 	radeon_ring_write(ring, 0xFFFFFFFF);
 	radeon_ring_write(ring, 0);
 	radeon_ring_write(ring, ((ib->vm ? ib->vm->id : 0) << 24) | 10); /* poll interval */
+
+	/* Flush HDP cache (for SI) */
+	WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
 }
 
 static void cayman_cp_enable(struct radeon_device *rdev, bool enable)
diff --git a/drivers/gpu/drm/radeon/ni_dma.c b/drivers/gpu/drm/radeon/ni_dma.c
index 119fc69..0e575ea 100644
--- a/drivers/gpu/drm/radeon/ni_dma.c
+++ b/drivers/gpu/drm/radeon/ni_dma.c
@@ -148,6 +148,8 @@  void cayman_dma_ring_ib_execute(struct radeon_device *rdev,
 	radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0));
 	radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF));
 
+	/* Flush HDP cache (for SI) */
+	WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
 }
 
 /**
diff --git a/drivers/gpu/drm/radeon/radeon_ring.c b/drivers/gpu/drm/radeon/radeon_ring.c
index 62e9e57..31ac4fd 100644
--- a/drivers/gpu/drm/radeon/radeon_ring.c
+++ b/drivers/gpu/drm/radeon/radeon_ring.c
@@ -206,7 +206,7 @@  int radeon_ib_pool_init(struct radeon_device *rdev)
 		r = radeon_sa_bo_manager_init(rdev, &rdev->ring_tmp_bo,
 					      RADEON_IB_POOL_SIZE*64*1024,
 					      RADEON_GPU_PAGE_SIZE,
-					      RADEON_GEM_DOMAIN_GTT,
+					      RADEON_GEM_DOMAIN_VRAM,
 					      RADEON_GEM_GTT_WC);
 	} else {
 		/* Without GPUVM, it's better to stick to cacheable GTT due