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[2/2] drm/sti: vtg fix CEA-861E video format timing error

Message ID 1433493226-22971-3-git-send-email-vincent.abriou@st.com (mailing list archive)
State New, archived
Headers show

Commit Message

Vincent Abriou June 5, 2015, 8:33 a.m. UTC
HDMI analyzer tests showed that Vsync and Hsync signal were not
compliant with the HDMI protocol.

HDMI_DELAY should be taken into account in the VTG Vsync
programming to reflect the 6 pixels shift introduced in the VTG
Hsync programming.

Signed-off-by: Vincent Abriou <vincent.abriou@st.com>
---
 drivers/gpu/drm/sti/sti_vtg.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)
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Patch

diff --git a/drivers/gpu/drm/sti/sti_vtg.c b/drivers/gpu/drm/sti/sti_vtg.c
index eda62c8..d21df0d 100644
--- a/drivers/gpu/drm/sti/sti_vtg.c
+++ b/drivers/gpu/drm/sti/sti_vtg.c
@@ -151,8 +151,11 @@  static void vtg_set_mode(struct sti_vtg *vtg,
 	tmp |= 1;
 	writel(tmp, vtg->regs + VTG_TOP_V_VD_1);
 	writel(tmp, vtg->regs + VTG_BOT_V_VD_1);
-	writel(0, vtg->regs + VTG_TOP_V_HD_1);
-	writel(0, vtg->regs + VTG_BOT_V_HD_1);
+
+	tmp = HDMI_DELAY << 16;
+	tmp |= HDMI_DELAY;
+	writel(tmp, vtg->regs + VTG_TOP_V_HD_1);
+	writel(tmp, vtg->regs + VTG_BOT_V_HD_1);
 
 	/* prepare VTG set 2 for for HD DCS */
 	tmp = (mode->hsync_end - mode->hsync_start) << 16;