| Message ID | 20200309195216.31042-8-laurent.pinchart@ideasonboard.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm: mxsfb: Add i.MX7 support | expand |
On 2020-03-09 20:52, Laurent Pinchart wrote: > The LCDC_CTRL register is located at address 0x0000. Some of the > accesses to the register simply use the mxsfb->base address. Reference > the LCDC_CTRL register explicitly instead to clarify the code. > > Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Stefan Agner <stefan@agner.ch> > --- > drivers/gpu/drm/mxsfb/mxsfb_crtc.c | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/mxsfb/mxsfb_crtc.c > b/drivers/gpu/drm/mxsfb/mxsfb_crtc.c > index be60c4021e2f..722bd9b4f5f9 100644 > --- a/drivers/gpu/drm/mxsfb/mxsfb_crtc.c > +++ b/drivers/gpu/drm/mxsfb/mxsfb_crtc.c > @@ -170,17 +170,17 @@ static int mxsfb_reset_block(struct > mxsfb_drm_private *mxsfb) > { > int ret; > > - ret = clear_poll_bit(mxsfb->base, MODULE_SFTRST); > + ret = clear_poll_bit(mxsfb->base + LCDC_CTRL, MODULE_SFTRST); > if (ret) > return ret; > > - writel(MODULE_CLKGATE, mxsfb->base + MXS_CLR_ADDR); > + writel(MODULE_CLKGATE, mxsfb->base + LCDC_CTRL + MXS_CLR_ADDR); > > - ret = clear_poll_bit(mxsfb->base, MODULE_SFTRST); > + ret = clear_poll_bit(mxsfb->base + LCDC_CTRL, MODULE_SFTRST); > if (ret) > return ret; > > - return clear_poll_bit(mxsfb->base, MODULE_CLKGATE); > + return clear_poll_bit(mxsfb->base + LCDC_CTRL, MODULE_CLKGATE); > } > > static dma_addr_t mxsfb_get_fb_paddr(struct mxsfb_drm_private *mxsfb)
diff --git a/drivers/gpu/drm/mxsfb/mxsfb_crtc.c b/drivers/gpu/drm/mxsfb/mxsfb_crtc.c index be60c4021e2f..722bd9b4f5f9 100644 --- a/drivers/gpu/drm/mxsfb/mxsfb_crtc.c +++ b/drivers/gpu/drm/mxsfb/mxsfb_crtc.c @@ -170,17 +170,17 @@ static int mxsfb_reset_block(struct mxsfb_drm_private *mxsfb) { int ret; - ret = clear_poll_bit(mxsfb->base, MODULE_SFTRST); + ret = clear_poll_bit(mxsfb->base + LCDC_CTRL, MODULE_SFTRST); if (ret) return ret; - writel(MODULE_CLKGATE, mxsfb->base + MXS_CLR_ADDR); + writel(MODULE_CLKGATE, mxsfb->base + LCDC_CTRL + MXS_CLR_ADDR); - ret = clear_poll_bit(mxsfb->base, MODULE_SFTRST); + ret = clear_poll_bit(mxsfb->base + LCDC_CTRL, MODULE_SFTRST); if (ret) return ret; - return clear_poll_bit(mxsfb->base, MODULE_CLKGATE); + return clear_poll_bit(mxsfb->base + LCDC_CTRL, MODULE_CLKGATE); } static dma_addr_t mxsfb_get_fb_paddr(struct mxsfb_drm_private *mxsfb)
The LCDC_CTRL register is located at address 0x0000. Some of the accesses to the register simply use the mxsfb->base address. Reference the LCDC_CTRL register explicitly instead to clarify the code. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> --- drivers/gpu/drm/mxsfb/mxsfb_crtc.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)