| Message ID | 20210317154352.732095-13-maxime@cerno.tech (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/vc4: hdmi: Add Support for the YUV output | expand |
Am 17.03.21 um 16:43 schrieb Maxime Ripard: > On BCM2711, the HDMI_CSC_CTL register value has been hardcoded to an > opaque value. Let's replace it with properly defined values. > > Signed-off-by: Maxime Ripard <maxime@cerno.tech> Acked-by: Thomas Zimmermann <tzimmermann@suse.de> > --- > drivers/gpu/drm/vc4/vc4_hdmi.c | 5 ++--- > drivers/gpu/drm/vc4/vc4_regs.h | 3 +++ > 2 files changed, 5 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c > index 9ba555d24187..b0e0cb533944 100644 > --- a/drivers/gpu/drm/vc4/vc4_hdmi.c > +++ b/drivers/gpu/drm/vc4/vc4_hdmi.c > @@ -528,12 +528,11 @@ static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, > static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, > const struct drm_display_mode *mode) > { > - u32 csc_ctl; > + u32 csc_ctl = VC5_MT_CP_CSC_CTL_ENABLE | VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM, > + VC5_MT_CP_CSC_CTL_MODE); > > HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, 0x354021); > > - csc_ctl = 0x07; /* RGB_CONVERT_MODE = custom matrix, || USE_RGB_TO_YCBCR */ > - > if (vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode)) { > /* CEA VICs other than #1 requre limited range RGB > * output unless overridden by an AVI infoframe. > diff --git a/drivers/gpu/drm/vc4/vc4_regs.h b/drivers/gpu/drm/vc4/vc4_regs.h > index be2c32a519b3..9d7c034c8b4f 100644 > --- a/drivers/gpu/drm/vc4/vc4_regs.h > +++ b/drivers/gpu/drm/vc4/vc4_regs.h > @@ -744,6 +744,9 @@ > # define VC4_HD_CSC_CTL_RGB2YCC BIT(1) > # define VC4_HD_CSC_CTL_ENABLE BIT(0) > > +# define VC5_MT_CP_CSC_CTL_ENABLE BIT(2) > +# define VC5_MT_CP_CSC_CTL_MODE_MASK VC4_MASK(1, 0) > + > # define VC4_DVP_HT_CLOCK_STOP_PIXEL BIT(1) > > /* HVS display list information. */ >
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c index 9ba555d24187..b0e0cb533944 100644 --- a/drivers/gpu/drm/vc4/vc4_hdmi.c +++ b/drivers/gpu/drm/vc4/vc4_hdmi.c @@ -528,12 +528,11 @@ static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, const struct drm_display_mode *mode) { - u32 csc_ctl; + u32 csc_ctl = VC5_MT_CP_CSC_CTL_ENABLE | VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM, + VC5_MT_CP_CSC_CTL_MODE); HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, 0x354021); - csc_ctl = 0x07; /* RGB_CONVERT_MODE = custom matrix, || USE_RGB_TO_YCBCR */ - if (vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode)) { /* CEA VICs other than #1 requre limited range RGB * output unless overridden by an AVI infoframe. diff --git a/drivers/gpu/drm/vc4/vc4_regs.h b/drivers/gpu/drm/vc4/vc4_regs.h index be2c32a519b3..9d7c034c8b4f 100644 --- a/drivers/gpu/drm/vc4/vc4_regs.h +++ b/drivers/gpu/drm/vc4/vc4_regs.h @@ -744,6 +744,9 @@ # define VC4_HD_CSC_CTL_RGB2YCC BIT(1) # define VC4_HD_CSC_CTL_ENABLE BIT(0) +# define VC5_MT_CP_CSC_CTL_ENABLE BIT(2) +# define VC5_MT_CP_CSC_CTL_MODE_MASK VC4_MASK(1, 0) + # define VC4_DVP_HT_CLOCK_STOP_PIXEL BIT(1) /* HVS display list information. */
On BCM2711, the HDMI_CSC_CTL register value has been hardcoded to an opaque value. Let's replace it with properly defined values. Signed-off-by: Maxime Ripard <maxime@cerno.tech> --- drivers/gpu/drm/vc4/vc4_hdmi.c | 5 ++--- drivers/gpu/drm/vc4/vc4_regs.h | 3 +++ 2 files changed, 5 insertions(+), 3 deletions(-)