| Message ID | 20230206-topic-sm8450-upstream-dp-controller-v2-3-529da2203659@linaro.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: dts: qcom: add DP Controller to SM8350 & SM8450 DTS | expand |
On 10/02/2023 12:34, Neil Armstrong wrote: > Add the Display Port controller subnode to the MDSS node. > > Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> > --- > arch/arm64/boot/dts/qcom/sm8350.dtsi | 82 +++++++++++++++++++++++++++++++++++- > 1 file changed, 80 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi > index d490ce84a022..eb636b7dffa7 100644 > --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi > @@ -2862,13 +2862,20 @@ ports { > > port@0 { > reg = <0>; > - dpu_intf1_out: endpoint { > - remote-endpoint = <&mdss_dsi0_in>; > + dpu_intf0_out: endpoint { > + remote-endpoint = <&mdss_dp_in>; No need to reorder these ports. Please add DP to the end. > }; > }; > > port@1 { > reg = <1>; > + dpu_intf1_out: endpoint { > + remote-endpoint = <&mdss_dsi0_in>; > + }; > + }; > + > + port@2 { > + reg = <2>; > dpu_intf2_out: endpoint { > remote-endpoint = <&mdss_dsi1_in>; > }; > @@ -2876,6 +2883,77 @@ dpu_intf2_out: endpoint { > }; > }; > > + mdss_dp: displayport-controller@ae90000 { > + compatible = "qcom,sm8350-dp"; > + reg = <0 0xae90000 0 0x200>, > + <0 0xae90200 0 0x200>, > + <0 0xae90400 0 0x600>, > + <0 0xae91000 0 0x400>; This will not validate against the schema. Please add p1 region at the end (I assume it is <0 0x0ae91400 0 0x400>). > + interrupt-parent = <&mdss>; > + interrupts = <12>; > + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, > + <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, > + <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, > + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; > + clock-names = "core_iface", > + "core_aux", > + "ctrl_link", > + "ctrl_link_iface", > + "stream_pixel"; > + > + assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, > + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; > + assigned-clock-parents = <&usb_1_qmpphy 1>, > + <&usb_1_qmpphy 2>; Please use defined names here and in the phys below > + > + phys = <&usb_1_qmpphy 1>; > + phy-names = "dp"; > + > + #sound-dai-cells = <0>; > + > + operating-points-v2 = <&dp_opp_table>; > + power-domains = <&rpmhpd SM8350_MMCX>; > + > + status = "disabled"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + mdss_dp_in: endpoint { > + remote-endpoint = <&dpu_intf0_out>; > + }; > + }; > + }; > + > + dp_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-160000000 { > + opp-hz = /bits/ 64 <160000000>; > + required-opps = <&rpmhpd_opp_low_svs>; > + }; > + > + opp-270000000 { > + opp-hz = /bits/ 64 <270000000>; > + required-opps = <&rpmhpd_opp_svs>; > + }; > + > + opp-540000000 { > + opp-hz = /bits/ 64 <540000000>; > + required-opps = <&rpmhpd_opp_svs_l1>; > + }; > + > + opp-810000000 { > + opp-hz = /bits/ 64 <810000000>; > + required-opps = <&rpmhpd_opp_nom>; > + }; > + }; > + }; > + > mdss_dsi0: dsi@ae94000 { > compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl"; > reg = <0 0x0ae94000 0 0x400>; >
On 10/02/2023 12:08, Dmitry Baryshkov wrote: > On 10/02/2023 12:34, Neil Armstrong wrote: >> Add the Display Port controller subnode to the MDSS node. >> >> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> >> --- >> arch/arm64/boot/dts/qcom/sm8350.dtsi | 82 +++++++++++++++++++++++++++++++++++- >> 1 file changed, 80 insertions(+), 2 deletions(-) >> >> diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi >> index d490ce84a022..eb636b7dffa7 100644 >> --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi >> @@ -2862,13 +2862,20 @@ ports { >> port@0 { >> reg = <0>; >> - dpu_intf1_out: endpoint { >> - remote-endpoint = <&mdss_dsi0_in>; >> + dpu_intf0_out: endpoint { >> + remote-endpoint = <&mdss_dp_in>; > > No need to reorder these ports. Please add DP to the end. Right, but I'll keep the dpu_intf0_out label for this port, but having dpu_intf1_out, dpu_intf2_out then dpu_intf0_out isn't very clean... > >> }; >> }; >> port@1 { >> reg = <1>; >> + dpu_intf1_out: endpoint { >> + remote-endpoint = <&mdss_dsi0_in>; >> + }; >> + }; >> + >> + port@2 { >> + reg = <2>; >> dpu_intf2_out: endpoint { >> remote-endpoint = <&mdss_dsi1_in>; >> }; >> @@ -2876,6 +2883,77 @@ dpu_intf2_out: endpoint { >> }; >> }; >> + mdss_dp: displayport-controller@ae90000 { >> + compatible = "qcom,sm8350-dp"; >> + reg = <0 0xae90000 0 0x200>, >> + <0 0xae90200 0 0x200>, >> + <0 0xae90400 0 0x600>, >> + <0 0xae91000 0 0x400>; > > This will not validate against the schema. Please add p1 region at the end (I assume it is <0 0x0ae91400 0 0x400>). > >> + interrupt-parent = <&mdss>; >> + interrupts = <12>; >> + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, >> + <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, >> + <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, >> + <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, >> + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; >> + clock-names = "core_iface", >> + "core_aux", >> + "ctrl_link", >> + "ctrl_link_iface", >> + "stream_pixel"; >> + >> + assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, >> + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; >> + assigned-clock-parents = <&usb_1_qmpphy 1>, >> + <&usb_1_qmpphy 2>; > > Please use defined names here and in the phys below Ack, will do in all the patches > >> + >> + phys = <&usb_1_qmpphy 1>; >> + phy-names = "dp"; >> + >> + #sound-dai-cells = <0>; >> + >> + operating-points-v2 = <&dp_opp_table>; >> + power-domains = <&rpmhpd SM8350_MMCX>; >> + >> + status = "disabled"; >> + >> + ports { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + port@0 { >> + reg = <0>; >> + mdss_dp_in: endpoint { >> + remote-endpoint = <&dpu_intf0_out>; >> + }; >> + }; >> + }; >> + >> + dp_opp_table: opp-table { >> + compatible = "operating-points-v2"; >> + >> + opp-160000000 { >> + opp-hz = /bits/ 64 <160000000>; >> + required-opps = <&rpmhpd_opp_low_svs>; >> + }; >> + >> + opp-270000000 { >> + opp-hz = /bits/ 64 <270000000>; >> + required-opps = <&rpmhpd_opp_svs>; >> + }; >> + >> + opp-540000000 { >> + opp-hz = /bits/ 64 <540000000>; >> + required-opps = <&rpmhpd_opp_svs_l1>; >> + }; >> + >> + opp-810000000 { >> + opp-hz = /bits/ 64 <810000000>; >> + required-opps = <&rpmhpd_opp_nom>; >> + }; >> + }; >> + }; >> + >> mdss_dsi0: dsi@ae94000 { >> compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl"; >> reg = <0 0x0ae94000 0 0x400>; >> >
On 10/02/2023 16:18, Neil Armstrong wrote: > On 10/02/2023 12:08, Dmitry Baryshkov wrote: >> On 10/02/2023 12:34, Neil Armstrong wrote: >>> Add the Display Port controller subnode to the MDSS node. >>> >>> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> >>> --- >>> arch/arm64/boot/dts/qcom/sm8350.dtsi | 82 >>> +++++++++++++++++++++++++++++++++++- >>> 1 file changed, 80 insertions(+), 2 deletions(-) >>> >>> diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi >>> b/arch/arm64/boot/dts/qcom/sm8350.dtsi >>> index d490ce84a022..eb636b7dffa7 100644 >>> --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi >>> +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi >>> @@ -2862,13 +2862,20 @@ ports { >>> port@0 { >>> reg = <0>; >>> - dpu_intf1_out: endpoint { >>> - remote-endpoint = <&mdss_dsi0_in>; >>> + dpu_intf0_out: endpoint { >>> + remote-endpoint = <&mdss_dp_in>; >> >> No need to reorder these ports. Please add DP to the end. > > Right, but I'll keep the dpu_intf0_out label for this port, > but having dpu_intf1_out, dpu_intf2_out then dpu_intf0_out isn't very > clean... I don't have a strong opinion here. I think we can ignore it.
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index d490ce84a022..eb636b7dffa7 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -2862,13 +2862,20 @@ ports { port@0 { reg = <0>; - dpu_intf1_out: endpoint { - remote-endpoint = <&mdss_dsi0_in>; + dpu_intf0_out: endpoint { + remote-endpoint = <&mdss_dp_in>; }; }; port@1 { reg = <1>; + dpu_intf1_out: endpoint { + remote-endpoint = <&mdss_dsi0_in>; + }; + }; + + port@2 { + reg = <2>; dpu_intf2_out: endpoint { remote-endpoint = <&mdss_dsi1_in>; }; @@ -2876,6 +2883,77 @@ dpu_intf2_out: endpoint { }; }; + mdss_dp: displayport-controller@ae90000 { + compatible = "qcom,sm8350-dp"; + reg = <0 0xae90000 0 0x200>, + <0 0xae90200 0 0x200>, + <0 0xae90400 0 0x600>, + <0 0xae91000 0 0x400>; + interrupt-parent = <&mdss>; + interrupts = <12>; + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; + assigned-clock-parents = <&usb_1_qmpphy 1>, + <&usb_1_qmpphy 2>; + + phys = <&usb_1_qmpphy 1>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + operating-points-v2 = <&dp_opp_table>; + power-domains = <&rpmhpd SM8350_MMCX>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dp_in: endpoint { + remote-endpoint = <&dpu_intf0_out>; + }; + }; + }; + + dp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + mdss_dsi0: dsi@ae94000 { compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl"; reg = <0 0x0ae94000 0 0x400>;
Add the Display Port controller subnode to the MDSS node. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 82 +++++++++++++++++++++++++++++++++++- 1 file changed, 80 insertions(+), 2 deletions(-)