| Message ID | 4c3be351dac862a07c30bc32d13de495f1674045.1594230107.git-series.maxime@cerno.tech (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/vc4: Support BCM2711 Display Pipeline | expand |
Hi Maxime On Wed, 8 Jul 2020 at 18:42, Maxime Ripard <maxime@cerno.tech> wrote: > > In vc5, the HVS has 6 outputs and 3 FIFOs (or channels), with > pixelvalves each being assigned to a given output, but each output can > then be muxed to feed from multiple FIFOs. > > Since vc4 had that entirely static, both were probably equivalent, but > since that changes, let's rename hvs_channel to hvs_output in the > vc4_crtc_data, since a pixelvalve is really connected to an output, and > not to a FIFO. > > Signed-off-by: Maxime Ripard <maxime@cerno.tech> Reviewed-by: Dave Stevenson <dave.stevenson@raspberrypi.com> > --- > drivers/gpu/drm/vc4/vc4_crtc.c | 8 ++++---- > drivers/gpu/drm/vc4/vc4_drv.h | 4 ++-- > drivers/gpu/drm/vc4/vc4_hvs.c | 2 +- > drivers/gpu/drm/vc4/vc4_txp.c | 2 +- > 4 files changed, 8 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c > index fdecaba77836..d3126fe04d9a 100644 > --- a/drivers/gpu/drm/vc4/vc4_crtc.c > +++ b/drivers/gpu/drm/vc4/vc4_crtc.c > @@ -775,7 +775,7 @@ static const struct drm_crtc_helper_funcs vc4_crtc_helper_funcs = { > > static const struct vc4_pv_data bcm2835_pv0_data = { > .base = { > - .hvs_channel = 0, > + .hvs_output = 0, > }, > .debugfs_name = "crtc0_regs", > .pixels_per_clock = 1, > @@ -787,7 +787,7 @@ static const struct vc4_pv_data bcm2835_pv0_data = { > > static const struct vc4_pv_data bcm2835_pv1_data = { > .base = { > - .hvs_channel = 2, > + .hvs_output = 2, > }, > .debugfs_name = "crtc1_regs", > .pixels_per_clock = 1, > @@ -799,7 +799,7 @@ static const struct vc4_pv_data bcm2835_pv1_data = { > > static const struct vc4_pv_data bcm2835_pv2_data = { > .base = { > - .hvs_channel = 1, > + .hvs_output = 1, > }, > .debugfs_name = "crtc2_regs", > .pixels_per_clock = 1, > @@ -862,7 +862,7 @@ int vc4_crtc_init(struct drm_device *drm, struct vc4_crtc *vc4_crtc, > drm_crtc_init_with_planes(drm, crtc, primary_plane, NULL, > crtc_funcs, NULL); > drm_crtc_helper_add(crtc, crtc_helper_funcs); > - vc4_crtc->channel = vc4_crtc->data->hvs_channel; > + vc4_crtc->channel = vc4_crtc->data->hvs_output; > drm_mode_crtc_set_gamma_size(crtc, ARRAY_SIZE(vc4_crtc->lut_r)); > drm_crtc_enable_color_mgmt(crtc, 0, false, crtc->gamma_size); > > diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b/drivers/gpu/drm/vc4/vc4_drv.h > index d80fc3bbb450..d1cf4c038180 100644 > --- a/drivers/gpu/drm/vc4/vc4_drv.h > +++ b/drivers/gpu/drm/vc4/vc4_drv.h > @@ -447,8 +447,8 @@ to_vc4_encoder(struct drm_encoder *encoder) > } > > struct vc4_crtc_data { > - /* Which channel of the HVS this pixelvalve sources from. */ > - int hvs_channel; > + /* Which output of the HVS this pixelvalve sources from. */ > + int hvs_output; > }; > > struct vc4_pv_data { > diff --git a/drivers/gpu/drm/vc4/vc4_hvs.c b/drivers/gpu/drm/vc4/vc4_hvs.c > index 091fdf4908aa..6fd9de1dc65a 100644 > --- a/drivers/gpu/drm/vc4/vc4_hvs.c > +++ b/drivers/gpu/drm/vc4/vc4_hvs.c > @@ -419,7 +419,7 @@ void vc4_hvs_mode_set_nofb(struct drm_crtc *crtc) > struct drm_display_mode *mode = &crtc->state->adjusted_mode; > bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE; > > - if (vc4_crtc->data->hvs_channel == 2) { > + if (vc4_crtc->data->hvs_output == 2) { > u32 dispctrl; > u32 dsp3_mux; > > diff --git a/drivers/gpu/drm/vc4/vc4_txp.c b/drivers/gpu/drm/vc4/vc4_txp.c > index a7c3af0005a0..f39d9900d027 100644 > --- a/drivers/gpu/drm/vc4/vc4_txp.c > +++ b/drivers/gpu/drm/vc4/vc4_txp.c > @@ -452,7 +452,7 @@ static irqreturn_t vc4_txp_interrupt(int irq, void *data) > } > > static const struct vc4_crtc_data vc4_txp_crtc_data = { > - .hvs_channel = 2, > + .hvs_output = 2, > }; > > static int vc4_txp_bind(struct device *dev, struct device *master, void *data) > -- > git-series 0.9.1
diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c index fdecaba77836..d3126fe04d9a 100644 --- a/drivers/gpu/drm/vc4/vc4_crtc.c +++ b/drivers/gpu/drm/vc4/vc4_crtc.c @@ -775,7 +775,7 @@ static const struct drm_crtc_helper_funcs vc4_crtc_helper_funcs = { static const struct vc4_pv_data bcm2835_pv0_data = { .base = { - .hvs_channel = 0, + .hvs_output = 0, }, .debugfs_name = "crtc0_regs", .pixels_per_clock = 1, @@ -787,7 +787,7 @@ static const struct vc4_pv_data bcm2835_pv0_data = { static const struct vc4_pv_data bcm2835_pv1_data = { .base = { - .hvs_channel = 2, + .hvs_output = 2, }, .debugfs_name = "crtc1_regs", .pixels_per_clock = 1, @@ -799,7 +799,7 @@ static const struct vc4_pv_data bcm2835_pv1_data = { static const struct vc4_pv_data bcm2835_pv2_data = { .base = { - .hvs_channel = 1, + .hvs_output = 1, }, .debugfs_name = "crtc2_regs", .pixels_per_clock = 1, @@ -862,7 +862,7 @@ int vc4_crtc_init(struct drm_device *drm, struct vc4_crtc *vc4_crtc, drm_crtc_init_with_planes(drm, crtc, primary_plane, NULL, crtc_funcs, NULL); drm_crtc_helper_add(crtc, crtc_helper_funcs); - vc4_crtc->channel = vc4_crtc->data->hvs_channel; + vc4_crtc->channel = vc4_crtc->data->hvs_output; drm_mode_crtc_set_gamma_size(crtc, ARRAY_SIZE(vc4_crtc->lut_r)); drm_crtc_enable_color_mgmt(crtc, 0, false, crtc->gamma_size); diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b/drivers/gpu/drm/vc4/vc4_drv.h index d80fc3bbb450..d1cf4c038180 100644 --- a/drivers/gpu/drm/vc4/vc4_drv.h +++ b/drivers/gpu/drm/vc4/vc4_drv.h @@ -447,8 +447,8 @@ to_vc4_encoder(struct drm_encoder *encoder) } struct vc4_crtc_data { - /* Which channel of the HVS this pixelvalve sources from. */ - int hvs_channel; + /* Which output of the HVS this pixelvalve sources from. */ + int hvs_output; }; struct vc4_pv_data { diff --git a/drivers/gpu/drm/vc4/vc4_hvs.c b/drivers/gpu/drm/vc4/vc4_hvs.c index 091fdf4908aa..6fd9de1dc65a 100644 --- a/drivers/gpu/drm/vc4/vc4_hvs.c +++ b/drivers/gpu/drm/vc4/vc4_hvs.c @@ -419,7 +419,7 @@ void vc4_hvs_mode_set_nofb(struct drm_crtc *crtc) struct drm_display_mode *mode = &crtc->state->adjusted_mode; bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE; - if (vc4_crtc->data->hvs_channel == 2) { + if (vc4_crtc->data->hvs_output == 2) { u32 dispctrl; u32 dsp3_mux; diff --git a/drivers/gpu/drm/vc4/vc4_txp.c b/drivers/gpu/drm/vc4/vc4_txp.c index a7c3af0005a0..f39d9900d027 100644 --- a/drivers/gpu/drm/vc4/vc4_txp.c +++ b/drivers/gpu/drm/vc4/vc4_txp.c @@ -452,7 +452,7 @@ static irqreturn_t vc4_txp_interrupt(int irq, void *data) } static const struct vc4_crtc_data vc4_txp_crtc_data = { - .hvs_channel = 2, + .hvs_output = 2, }; static int vc4_txp_bind(struct device *dev, struct device *master, void *data)
In vc5, the HVS has 6 outputs and 3 FIFOs (or channels), with pixelvalves each being assigned to a given output, but each output can then be muxed to feed from multiple FIFOs. Since vc4 had that entirely static, both were probably equivalent, but since that changes, let's rename hvs_channel to hvs_output in the vc4_crtc_data, since a pixelvalve is really connected to an output, and not to a FIFO. Signed-off-by: Maxime Ripard <maxime@cerno.tech> --- drivers/gpu/drm/vc4/vc4_crtc.c | 8 ++++---- drivers/gpu/drm/vc4/vc4_drv.h | 4 ++-- drivers/gpu/drm/vc4/vc4_hvs.c | 2 +- drivers/gpu/drm/vc4/vc4_txp.c | 2 +- 4 files changed, 8 insertions(+), 8 deletions(-)