mbox series

[00/12] drm/i915: Clean up the wm mem latency stuff

Message ID 20181010130454.28557-1-ville.syrjala@linux.intel.com (mailing list archive)
Headers show
Series drm/i915: Clean up the wm mem latency stuff | expand

Message

Ville Syrjala Oct. 10, 2018, 1:04 p.m. UTC
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Currently we store the watermark memory latency values in three
different units (.1 usec, .5 usec, and 1 usec). Let's make things
less confusing by picking .1 usec as the one true unit and unify
all platforms around that. And I've included some other cleanups
related to this latency stuff.

Ville Syrjälä (12):
  drm/i915: Store all wm memory latency values in .1 usec units
  drm/i915: Use the spr/cur latencies on vlv/chv/g4x
  drm/i915: Eliminate skl_latency[]
  drm/i915: Add dev_priv->wm.num_levels and use it everywhere
  drm/i915: Add DEFINE_SNPRINTF_ARRAY()
  drm/i915: Make the WM memory latency print more compact
  drm/i915: Eliminate redundant ilk sprite/cursor wm fixup code
  drm/i915: Split skl+ and ilk+ read_wm_latency()
  drm/i915: Sanitize wm latency values for ilk+
  drm/i915: Drop the funky ilk wm setup
  drm/i915: Allow LP3 watermarks on ILK
  drm/i915: Remove the remnants of the ilk+ LP0 wm hack

 drivers/gpu/drm/i915/i915_debugfs.c  |  82 +---
 drivers/gpu/drm/i915/i915_drv.h      |  26 +-
 drivers/gpu/drm/i915/i915_utils.h    |  16 +
 drivers/gpu/drm/i915/intel_display.c |  12 +-
 drivers/gpu/drm/i915/intel_dp.c      |  17 +-
 drivers/gpu/drm/i915/intel_pm.c      | 587 ++++++++++++++-------------
 6 files changed, 349 insertions(+), 391 deletions(-)