mbox series

[v3,0/7] Fix ctx workarounds for non-masked regs

Message ID 20230630203509.1635216-1-lucas.demarchi@intel.com (mailing list archive)
Headers show
Series Fix ctx workarounds for non-masked regs | expand

Message

Lucas De Marchi June 30, 2023, 8:35 p.m. UTC
v3 of https://patchwork.freedesktop.org/series/119766/

Changes from v2:

	- Do not rmw if (clr | set) covers all bits
	- Add patch to make sure the set bits are also checked on
	  wa_*_clr_set() when clr is not a superset.

Tested on DG2 with intel_reg reading 0xb158 with a busy render engine.
Now it's not losing the upper bit anymore.

Lucas De Marchi (7):
  drm/i915/gt: Move wal_get_fw_for_rmw()
  drm/i915/gt: Clear all bits from GEN12_FF_MODE2
  drm/i915/gt: Fix context workarounds with non-masked regs
  drm/i915/gt: Drop read from GEN8_L3CNTLREG in ICL workaround
  drm/i915/gt: Enable read back on XEHP_FF_MODE2
  drm/i915/gt: Remove bogus comment on IVB_FBC_RT_BASE_UPPER
  drm/i915/gt: Also check set bits in clr_set()

 drivers/gpu/drm/i915/gt/intel_workarounds.c | 129 ++++++++++----------
 1 file changed, 66 insertions(+), 63 deletions(-)

Comments

Kenneth Graunke July 1, 2023, 12:41 a.m. UTC | #1
On Friday, June 30, 2023 1:35:02 PM PDT Lucas De Marchi wrote:
> v3 of https://patchwork.freedesktop.org/series/119766/
> 
> Changes from v2:
> 
> 	- Do not rmw if (clr | set) covers all bits
> 	- Add patch to make sure the set bits are also checked on
> 	  wa_*_clr_set() when clr is not a superset.
> 
> Tested on DG2 with intel_reg reading 0xb158 with a busy render engine.
> Now it's not losing the upper bit anymore.
> 
> Lucas De Marchi (7):
>   drm/i915/gt: Move wal_get_fw_for_rmw()
>   drm/i915/gt: Clear all bits from GEN12_FF_MODE2
>   drm/i915/gt: Fix context workarounds with non-masked regs
>   drm/i915/gt: Drop read from GEN8_L3CNTLREG in ICL workaround
>   drm/i915/gt: Enable read back on XEHP_FF_MODE2
>   drm/i915/gt: Remove bogus comment on IVB_FBC_RT_BASE_UPPER
>   drm/i915/gt: Also check set bits in clr_set()
> 
>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 129 ++++++++++----------
>  1 file changed, 66 insertions(+), 63 deletions(-)

Whole series is now:

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

Thanks a lot for fixing this, Lucas!
Lucas De Marchi July 3, 2023, 6:41 p.m. UTC | #2
On Fri, Jun 30, 2023 at 05:41:21PM -0700, Kenneth Graunke wrote:
>On Friday, June 30, 2023 1:35:02 PM PDT Lucas De Marchi wrote:
>> v3 of https://patchwork.freedesktop.org/series/119766/
>>
>> Changes from v2:
>>
>> 	- Do not rmw if (clr | set) covers all bits
>> 	- Add patch to make sure the set bits are also checked on
>> 	  wa_*_clr_set() when clr is not a superset.
>>
>> Tested on DG2 with intel_reg reading 0xb158 with a busy render engine.
>> Now it's not losing the upper bit anymore.
>>
>> Lucas De Marchi (7):
>>   drm/i915/gt: Move wal_get_fw_for_rmw()
>>   drm/i915/gt: Clear all bits from GEN12_FF_MODE2
>>   drm/i915/gt: Fix context workarounds with non-masked regs
>>   drm/i915/gt: Drop read from GEN8_L3CNTLREG in ICL workaround
>>   drm/i915/gt: Enable read back on XEHP_FF_MODE2
>>   drm/i915/gt: Remove bogus comment on IVB_FBC_RT_BASE_UPPER
>>   drm/i915/gt: Also check set bits in clr_set()
>>
>>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 129 ++++++++++----------
>>  1 file changed, 66 insertions(+), 63 deletions(-)
>
>Whole series is now:
>
>Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
>
>Thanks a lot for fixing this, Lucas!

Thanks for the detailed review and help fixing this.
All patches pushed to drm-intel-gt-next branch. Later this week I will
work on getting the important fix backported to the relevant stable
trees.

Lucas De Marchi