Show patches with: Search = vlv       |   1295 patches
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Patch Series A/R/T S/W/F Date Submitter Delegate State
[v2,12/25] drm/i915: vlv: check port power domain instead of only D0 for eDP VDD on - - - --- 2014-04-14 Imre Deak New
[v2,03/25] drm/i915: vlv: add RC6 residency counters - - - --- 2014-04-14 Imre Deak New
[v2,02/25] drm/i915: vlv: clear master interrupt flag when disabling interrupts - - - --- 2014-04-14 Imre Deak New
[v2,01/25] drm/i915: vlv: clean up GTLC wake control/status register macros - - - --- 2014-04-14 Imre Deak New
[v5,2/6] drm/i915/vlv: Added a rendering specific Hw WA 'WaSendDummy3dPrimitveAfterSetContext' - - - --- 2014-04-14 sourab.gupta@intel.com New
drm/i915/vlv: assert and de-assert sideband reset on resume - - - --- 2014-04-11 Jesse Barnes New
[50/71] drm/i915/chv: Clarify VLV/CHV PIPESTAT bits a bit more - - - --- 2014-04-09 Ville Syrjälä New
[18/71] drm/i915/chv: Add vlv_pipe_to_channel - - - --- 2014-04-09 Ville Syrjälä New
[15/15] drm/i915: vlv: enable RPM - - - --- 2014-04-08 Imre Deak New
[14/15] drm/i915: vlv: add runtime PM support - - - --- 2014-04-08 Imre Deak New
[13/15] drm/i915: vlv: add gunit s0ix save/restore helpers - - - --- 2014-04-08 Imre Deak New
[11/15] drm/i915: vlv: disable RPM if RC6 is not enabled - - - --- 2014-04-08 Imre Deak New
[09/15] drm/i915: vlv: factor out vlv_force_gfx_clock - - - --- 2014-04-08 Imre Deak New
[08/15] drm/i915: vlv: setup RPS min/max frequencies once during init time - - - --- 2014-04-08 Imre Deak New
[07/15] drm/i915: vlv: check port power domain instead of only D0 for eDP VDD on - - - --- 2014-04-08 Imre Deak New
[03/15] drm/i915: vlv: add RC6 residency counters - - - --- 2014-04-08 Imre Deak New
[02/15] drm/i915: vlv: clear master interrupt flag when disabling interrupts - - - --- 2014-04-08 Imre Deak New
[01/15] drm/i915: vlv: clean up GTLC wake control/status register macros - - - --- 2014-04-08 Imre Deak New
[6/6] drm/i915/vlv: re-order TX lane reset per latest spec - - - --- 2014-04-04 Jesse Barnes New
[5/6] drm/i915/vlv: move DP enable after plane/pipe enable per latest spec - - - --- 2014-04-04 Jesse Barnes New
[v4,5/6] drm/i915/vlv:Implement the WA 'WaDisable_RenderCache_OperationalFlush' - - - --- 2014-04-04 sourab.gupta@intel.com New
drm/i915: vlv: fix RPS interrupt mask setting - - - --- 2014-04-03 Imre Deak New
[v2] Revert "drm/i915/vlv: fixup DDR freq detection per Punit spec" - - - --- 2014-04-03 deepak.s@linux.intel.com New
[v3,5/6] drm/i915/vlv:Implement the WA 'WaDisable_RenderCache_OperationalFlush' - - - --- 2014-04-03 sourab.gupta@intel.com New
[3/4] drm/i915: enable HDMI mode on VLV when an HDMI sink is detected - - - --- 2014-04-02 Jesse Barnes New
[2/4] drm/i915/vlv: disable AVI infoframe emission when writing infoframes - - - --- 2014-04-02 Jesse Barnes New
[1/4] drm/i915/vlv: write the port field in the per-pipe DIP control reg - - - --- 2014-04-02 Jesse Barnes New
[3/3] drm/i915/vlv: use min brightness from VBT - - - --- 2014-03-31 Jesse Barnes New
drm/i915: vlv: reserve the GT power context only once during driver init - - - --- 2014-03-31 Imre Deak New
Revert "drm/i915/vlv: fixup DDR freq detection per Punit spec" - - - --- 2014-03-30 deepak.s@linux.intel.com New
[v6] drm/i915/vlv: WA for Turbo and RC6 to work together. - - - --- 2014-03-30 deepak.s@linux.intel.com New
[1/2] drm/i915: Hide vlv_force_wake_{get, put}() in intel_uncore.c - - - --- 2014-03-28 Lespiau, Damien New
[6/6] drm/i915: Support for RR switching on VLV - - - --- 2014-03-28 vandana.kannan@intel.com New
drm/i915/vlv: use W_SYNC_SHIFT for interlaced modes on VLV - - - --- 2014-03-27 Jesse Barnes New
[2/2] drm/i915: vlv: get power domain for eDP vdd - - - --- 2014-03-27 Imre Deak New
[1/2] drm/i915: vlv: cache current CD clock rate - - - --- 2014-03-27 Imre Deak New
drm/i915: Mask PM interrupt generation when at up/down limits for VLV - - - --- 2014-03-27 Chris Wilson New
[v5] drm/i915/vlv: WA for Turbo and RC6 to work together. - - - --- 2014-03-27 deepak.s@linux.intel.com New
[v6] drm/i915/vlv: Added a rendering specific Hw WA 'WaTlbInvalidateStoreDataBefore' - - - --- 2014-03-25 sourab.gupta@intel.com New
[v5] drm/i915/vlv: Added a rendering specific Hw WA 'WaTlbInvalidateStoreDataBefore' - - - --- 2014-03-25 sourab.gupta@intel.com New
[v2,4/6] drm/i915/vlv: Remove the enabling of VS_TIMER_DISPATCH bit in MI MODE reg - - - --- 2014-03-24 sourab.gupta@intel.com New
[v2,6/6] drm/i915/vlv: Modifying WA 'WaDisableL3Bank2xClockGate for vlv - - - --- 2014-03-24 sourab.gupta@intel.com New
[v2,5/6] drm/i915/vlv:Implement the WA 'WaDisable_RenderCache_OperationalFlush' - - - --- 2014-03-24 sourab.gupta@intel.com New
[4/6] drm/i915/vlv: Remove the enabling of VS_TIMER_DISPATCH bit in MI MODE reg - - - --- 2014-03-24 sourab.gupta@intel.com New
[v4,2/6] drm/i915/vlv: Added a rendering specific Hw WA 'WaSendDummy3dPrimitveAfterSetContext' - - - --- 2014-03-24 sourab.gupta@intel.com New
[v4,1/6] drm/i915/vlv: Added a rendering specific Hw WA 'WaTlbInvalidateStoreDataBefore' - - - --- 2014-03-24 sourab.gupta@intel.com New
[6/6] drm/i915/vlv: Modified Implementation of WaDisableL3Bank2xClockGate - - - --- 2014-03-24 sourab.gupta@intel.com New
[5/6] drm/i915/vlv:Implement WaDisable_RenderCache_OperationalFlush - - - --- 2014-03-24 sourab.gupta@intel.com New
[4/6] drm/i915/vlv: Remove the enabling of VS_TIMER_DISPATCH bit in MI MODE reg - - - --- 2014-03-24 sourab.gupta@intel.com New
[2/6] drm/i915/vlv: Added a rendering specific Hw WA 'WaSendDummy3dPrimitveAfterSetContext' - - - --- 2014-03-24 sourab.gupta@intel.com New
[1/6] drm/i915/vlv: Added a rendering specific Hw WA 'WaTlbInvalidateStoreDataBefore' - - - --- 2014-03-24 sourab.gupta@intel.com New
[v3] drm/i915: Replaced Blitter ring based flips with MMIO flips for VLV - - - --- 2014-03-23 sourab.gupta@intel.com New
[v2] drm/i915: Replaced Blitter ring based flips with MMIO flips for VLV - - - --- 2014-03-21 sourab.gupta@intel.com New
[v2] drm/i915/vlv: Enabling the TLB invalidate bit in GFX Mode register - - - --- 2014-03-21 sourab.gupta@intel.com New
[v3] drm/i915/vlv: Added a rendering specific Hw WA 'WaSendDummy3dPrimitveAfterSetContext' - - - --- 2014-03-21 sourab.gupta@intel.com New
[2/2] drm/i915/vlv: Modified Implementation of WaDisableL3Bank2xClockGate - - - --- 2014-03-21 sourab.gupta@intel.com New
[1/2] drm/i915/vlv:Implement WaDisable_RenderCache_OperationalFlush - - - --- 2014-03-21 sourab.gupta@intel.com New
[2/2] drm/i915/vlv: Enabling the TLB invalidate bit in GFX Mode register - - - --- 2014-03-21 sourab.gupta@intel.com New
[1/2] drm/i915/vlv: Remove the enabling of VS_TIMER_DISPATCH bit in MI MODE reg - - - --- 2014-03-21 sourab.gupta@intel.com New
[v3] drm/i915/vlv: Added a rendering specific Hw WA 'WaTlbInvalidateStoreDataBefore' - - - --- 2014-03-21 sourab.gupta@intel.com New
[v2] drm/i915: Replaced Blitter ring based flips with MMIO flips for VLV - - - --- 2014-03-17 sourab.gupta@intel.com New
[v4,2/3] drm/i915/vlv: WA for Turbo and RC6 to work together. - - - --- 2014-03-15 deepak.s@linux.intel.com New
drm/i915: Remove erronous WARN in the vlv pipe crc code - - - --- 2014-03-13 Daniel Vetter New
[v3,2/3] drm/i915/vlv: WA for Turbo and RC6 to work together. - - - --- 2014-03-13 deepak.s@linux.intel.com New
[v2] drm/i915: Replaced Blitter ring based flips with MMIO flips for VLV - - - --- 2014-03-13 sourab.gupta@intel.com New
drm/i915: Replaced Blitter ring based flips with MMIO flips for VLV - - - --- 2014-03-13 sourab.gupta@intel.com New
drm/i915: fix vxd392 memory corruption on VLV and >4GB - - - --- 2014-03-08 Kelley, Sean V New
[6/6] drm/i915: Support for RR switching on VLV - - - --- 2014-03-07 vandana.kannan@intel.com New
[v3,21/21] drm/i915: power domains: add vlv power wells - - - --- 2014-03-05 Imre Deak New
[RFC,2/3] i915/drm: Increase the utilization of stolen memory on VLV - - - --- 2014-03-05 sourab.gupta@intel.com New
[6/6] drm/i915: Support for RR switching on VLV - - - --- 2014-03-05 vandana.kannan@intel.com New
[v2,21/21] drm/i915: power domains: add vlv power wells - - - --- 2014-03-04 Imre Deak New
[v2,18/21] drm/i915: vlv: factor out valleyview_display_irq_install - - - --- 2014-03-04 Imre Deak New
[v2,12/21] drm/i915: vlv: keep first level vblank IRQs masked - - - --- 2014-03-04 Imre Deak New
drm/i915/vlv: no MCHBAR on VLV - - - --- 2014-03-03 Jesse Barnes New
[v4] drm/i915: add support for Z-order of planes for VLV. - - - --- 2014-03-03 yu.dai@intel.com New
[v2] drm/i915/vlv: WA for Turbo and RC6 to work together. - - - --- 2014-03-03 deepak.s@intel.com New
drm/i915: Fix drain latency precision multipler for VLV - - - --- 2014-02-27 Zhenyu Wang New
[v3] drm/i915: add support for Z-order of planes for VLV. - - - --- 2014-02-27 yu.dai@intel.com New
[3/2] drm/i915: Streamline VLV forcewake handling - - - --- 2014-02-27 Ville Syrjälä New
[2/2] drm/i915: Drop the forcewake count inc/dec around register read on VLV - - - --- 2014-02-24 Ville Syrjälä New
[1/2] drm/i915: Fix VLV forcewake after reset - - - --- 2014-02-24 Ville Syrjälä New
[19/19] drm/i915: power domains: add vlv power wells - - - --- 2014-02-17 Imre Deak New
[17/19] drm/i915: vlv: factor out valleyview_display_irq_install - - - --- 2014-02-17 Imre Deak New
[11/19] drm/i915: vlv: keep first level vblank IRQs masked - - - --- 2014-02-17 Imre Deak New
drm/i915: vlv: reserve GT power context early - - - --- 2014-02-11 Imre Deak New
[v2,3/3] drm/i915: vlv: handle only enabled pipestat interrupt events - - - --- 2014-02-10 Imre Deak New
[v2,2/3] drm/i915: vlv: fix mapping of pipestat enable to status bits - - - --- 2014-02-10 Imre Deak New
[v2] drm/i915/vlv: Added a rendering specific Hw WA 'WaSendDummy3dPrimitveAfterSetContext' - - - --- 2014-02-08 akash.goel@intel.com New
[v2,3/3] drm/i915/vlv: Modified the programming of 2 regs in Ring initialisation - - - --- 2014-02-07 akash.goel@intel.com New
[v2,2/3] drm/i915/vlv: Added a rendering specific Hw WA 'WaReadAfterWriteHazard' - - - --- 2014-02-07 akash.goel@intel.com New
[v2,1/3] drm/i915/vlv: Added a rendering specific Hw WA 'WaTlbInvalidateStoreDataBefore' - - - --- 2014-02-07 akash.goel@intel.com New
drm/i915/vlv: Added write-enable pte bit support - - - --- 2014-02-06 akash.goel@intel.com New
[v3,6/7] drm/i915: vlv: fix mapping of pipestat enable to status bits - - - --- 2014-02-05 Imre Deak New
[v2,7/7] drm/i915: vlv: handle only enabled pipestat interrupt events - - - --- 2014-02-05 Imre Deak New
[v2,6/7] drm/i915: vlv: fix mapping of pipestat enable to status bits - - - --- 2014-02-05 Imre Deak New
[7/7] drm/i915: vlv: handle only enabled pipestat interrupt events - - - --- 2014-02-04 Imre Deak New
[6/7] drm/i915: vlv: fix mapping of pipestat enable to status bits - - - --- 2014-02-04 Imre Deak New
[3/7] drm/i915: vlv: s/spin_lock_irqsave/spin_lock/ in irq handler - - - --- 2014-02-04 Imre Deak New
[1/7] drm/i915: vlv: don't unmask IIR[DISPLAY_PIPE_A/B_VBLANK] interrupt - - - --- 2014-02-04 Imre Deak New
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