Show patches with: Series = Tiger Lake batch 3       |    State = Action Required       |   39 patches
Patch Series A/R/T S/W/F Date Submitter Delegate State
[39/39] drm/i915/tgl: Gen-12 media compression Tiger Lake batch 3 - - - --- 2019-08-16 Lucas De Marchi New
[38/39] drm/framebuffer/tgl: Format modifier for Intel Gen-12 media compression Tiger Lake batch 3 - - - --- 2019-08-16 Lucas De Marchi New
[37/39] drm/i915/tgl: Gen-12 render decompression Tiger Lake batch 3 - - - --- 2019-08-16 Lucas De Marchi New
[36/39] drm/framebuffer/tgl: Format modifier for Intel Gen-12 render compression Tiger Lake batch 3 - - - --- 2019-08-16 Lucas De Marchi New
[35/39] drm/i915/tgl: Gen-12 display loses Yf tiling and legacy CCS support Tiger Lake batch 3 - - - --- 2019-08-16 Lucas De Marchi New
[34/39] drm/i915/tgl: Add perf support on TGL Tiger Lake batch 3 - - - --- 2019-08-16 Lucas De Marchi New
[33/39] drm/i915/perf: add a parameter to control the size of OA buffer Tiger Lake batch 3 - 1 - --- 2019-08-16 Lucas De Marchi New
[32/39] drm/i915/tgl/perf: use the same oa ctx_id format as icl Tiger Lake batch 3 - 1 - --- 2019-08-16 Lucas De Marchi New
[31/39] drm/i915/tgl: Updated Private PAT programming Tiger Lake batch 3 - - - --- 2019-08-16 Lucas De Marchi New
[30/39] drm/i915/tgl: Move GTCR register to cope with GAM MMIO address remap Tiger Lake batch 3 - - - --- 2019-08-16 Lucas De Marchi New
[29/39] drm/i915/tgl: Report valid VDBoxes with SFC capability Tiger Lake batch 3 - - - --- 2019-08-16 Lucas De Marchi New
[28/39] drm/i915/tgl: add GEN12_MAX_CONTEXT_HW_ID Tiger Lake batch 3 - - - --- 2019-08-16 Lucas De Marchi New
[27/39] drm/i915/tgl: add Gen12 default indirect ctx offset Tiger Lake batch 3 - 1 - --- 2019-08-16 Lucas De Marchi New
[26/39] HACK: drm/i915/tgl: Gen12 render context size Tiger Lake batch 3 - - - --- 2019-08-16 Lucas De Marchi New
[25/39] drm/i915/tgl: Implement TGL DisplayPort training sequence Tiger Lake batch 3 - - - --- 2019-08-16 Lucas De Marchi New
[24/39] drm/i915/tgl: move DP_TP_* to transcoder Tiger Lake batch 3 - - - --- 2019-08-16 Lucas De Marchi New
[23/39] drm/i915/tgl: Register state context definition for Gen12 Tiger Lake batch 3 - 1 - --- 2019-08-16 Lucas De Marchi New
[22/39] drm/i915/tgl: implement WaProgramMgsrForCorrectSliceSpecificMmioReads Tiger Lake batch 3 - - - --- 2019-08-16 Lucas De Marchi New
[21/39] drm/i915/tgl: Do not apply WaIncreaseDefaultTLBEntries from GEN12 onwards Tiger Lake batch 3 - - - --- 2019-08-16 Lucas De Marchi New
[20/39] drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gating Tiger Lake batch 3 - - - --- 2019-08-16 Lucas De Marchi New
[19/39] drm/i915/tgl: Implement Wa_1406941453 Tiger Lake batch 3 - 3 - --- 2019-08-16 Lucas De Marchi New
[18/39] drm/i915/tgl: Introduce initial Tiger Lake workarounds Tiger Lake batch 3 - 1 - --- 2019-08-16 Lucas De Marchi New
[17/39] drm/i915/tgl: Select master transcoder in DP MST Tiger Lake batch 3 - - - --- 2019-08-16 Lucas De Marchi New
[16/39] drm/i915: Disable pipes in reverse order Tiger Lake batch 3 - - - --- 2019-08-16 Lucas De Marchi New
[15/39] drm: Add for_each_oldnew_intel_crtc_in_state_reverse() Tiger Lake batch 3 - - - --- 2019-08-16 Lucas De Marchi New
[14/39] drm/i915: Add for_each_new_intel_connector_in_state() Tiger Lake batch 3 - 1 - --- 2019-08-16 Lucas De Marchi New
[13/39] drm/i915/mst: Do not hardcoded the crtcs that encoder can connect Tiger Lake batch 3 - - - --- 2019-08-16 Lucas De Marchi New
[12/39] drm/i915/tgl: Add maximum resolution supported by PSR2 HW Tiger Lake batch 3 - - - --- 2019-08-16 Lucas De Marchi New
[11/39] drm/i915/tgl: Access the right register when handling PSR interruptions Tiger Lake batch 3 - - - --- 2019-08-16 Lucas De Marchi New
[10/39] drm/i915/tgl: PSR link standby is not supported anymore Tiger Lake batch 3 - 1 - --- 2019-08-16 Lucas De Marchi New
[09/39] drm/i915: Do not read PSR2 register in transcoders without PSR2 Tiger Lake batch 3 - - - --- 2019-08-16 Lucas De Marchi New
[08/39] drm/i915/tgl: Change PSR2 transcoder restriction Tiger Lake batch 3 - - - --- 2019-08-16 Lucas De Marchi New
[07/39] drm/i915: Guard and warn if more than one eDP panel is present Tiger Lake batch 3 - - - --- 2019-08-16 Lucas De Marchi New
[06/39] drm/i915/bdw+: Enable PSR in any eDP port Tiger Lake batch 3 - 1 - --- 2019-08-16 Lucas De Marchi New
[05/39] drm/i915/psr: Only handle interruptions of the transcoder in use Tiger Lake batch 3 - - - --- 2019-08-16 Lucas De Marchi New
[04/39] drm/i915: Do not unmask PSR interruption in IRQ postinstall Tiger Lake batch 3 - - - --- 2019-08-16 Lucas De Marchi New
[03/39] drm/i915: Add transcoder restriction to PSR2 Tiger Lake batch 3 - - - --- 2019-08-16 Lucas De Marchi New
[02/39] drm/i915/psr: Make PSR registers relative to transcoders Tiger Lake batch 3 - - - --- 2019-08-16 Lucas De Marchi New
[01/39] drm/i915/tgl: do not use DDIC Tiger Lake batch 3 - 1 - --- 2019-08-16 Lucas De Marchi New