Show patches with: Series = Begin enabling Xe_HP SDV and DG2 platforms       |   53 patches
Patch Series A/R/T S/W/F Date Submitter Delegate State
[53/53] drm/i915/dg2: Configure PCON in DP pre-enable path Begin enabling Xe_HP SDV and DG2 platforms - - - --- 2021-07-01 Matt Roper New
[52/53] drm/i915/dg2: Update to bigjoiner path Begin enabling Xe_HP SDV and DG2 platforms - 1 - --- 2021-07-01 Matt Roper New
[51/53] drm/i915/display/dsc: Set BPP in the kernel Begin enabling Xe_HP SDV and DG2 platforms - - - --- 2021-07-01 Matt Roper New
[50/53] drm/i915/display/dsc: Add Per connector debugfs node for DSC BPP enable Begin enabling Xe_HP SDV and DG2 platforms - - - --- 2021-07-01 Matt Roper New
[49/53] drm/i915/dg2: Add DG2 to the PSR2 defeature list Begin enabling Xe_HP SDV and DG2 platforms - - - --- 2021-07-01 Matt Roper New
[48/53] drm/i915/dg2: Update lane disable power state during PSR Begin enabling Xe_HP SDV and DG2 platforms - - - --- 2021-07-01 Matt Roper New
[47/53] drm/i915/dg2: Wait for SNPS PHY calibration during display init Begin enabling Xe_HP SDV and DG2 platforms - - - --- 2021-07-01 Matt Roper New
[46/53] drm/i915/dg2: Classify DG2 PHY types Begin enabling Xe_HP SDV and DG2 platforms - - - --- 2021-07-01 Matt Roper New
[45/53] drm/i915/dg2: Update modeset sequences Begin enabling Xe_HP SDV and DG2 platforms - - - --- 2021-07-01 Matt Roper New
[44/53] drm/i915/dg2: Add vswing programming for SNPS phys Begin enabling Xe_HP SDV and DG2 platforms - - - --- 2021-07-01 Matt Roper New
[43/53] drm/i915/dg2: Add MPLLB programming for HDMI Begin enabling Xe_HP SDV and DG2 platforms - - - --- 2021-07-01 Matt Roper New
[42/53] drm/i915/dg2: Add MPLLB programming for SNPS PHY Begin enabling Xe_HP SDV and DG2 platforms - - - --- 2021-07-01 Matt Roper New
[41/53] drm/i915/dg2: DG2 has fixed memory bandwidth Begin enabling Xe_HP SDV and DG2 platforms - - - --- 2021-07-01 Matt Roper New
[40/53] drm/i915/dg2: Don't read DRAM info Begin enabling Xe_HP SDV and DG2 platforms - - - --- 2021-07-01 Matt Roper New
[39/53] drm/i915/dg2: Don't program BW_BUDDY registers Begin enabling Xe_HP SDV and DG2 platforms - - - --- 2021-07-01 Matt Roper New
[38/53] drm/i915/dg2: Add dbuf programming Begin enabling Xe_HP SDV and DG2 platforms - - - --- 2021-07-01 Matt Roper New
[37/53] drm/i915/dg2: Setup display outputs Begin enabling Xe_HP SDV and DG2 platforms - - - --- 2021-07-01 Matt Roper New
[36/53] drm/i915/dg2: Don't wait for AUX power well enable ACKs Begin enabling Xe_HP SDV and DG2 platforms - - - --- 2021-07-01 Matt Roper New
[35/53] drm/i915/dg2: Skip shared DPLL handling Begin enabling Xe_HP SDV and DG2 platforms - - - --- 2021-07-01 Matt Roper New
[34/53] drm/i915/dg2: Add cdclk table and reference clock Begin enabling Xe_HP SDV and DG2 platforms - - - --- 2021-07-01 Matt Roper New
[33/53] drm/i915/dg2: Add fake PCH Begin enabling Xe_HP SDV and DG2 platforms - 1 - --- 2021-07-01 Matt Roper New
[32/53] drm/i915/dg2: Define MOCS table for DG2 Begin enabling Xe_HP SDV and DG2 platforms - - - --- 2021-07-01 Matt Roper New
[31/53] drm/i915/dg2: Report INSTDONE_GEOM values in error state Begin enabling Xe_HP SDV and DG2 platforms 1 - - --- 2021-07-01 Matt Roper New
[30/53] drm/i915/dg2: Maintain backward-compatible nested batch behavior Begin enabling Xe_HP SDV and DG2 platforms - - - --- 2021-07-01 Matt Roper New
[29/53] drm/i915/dg2: Add new LRI reg offsets Begin enabling Xe_HP SDV and DG2 platforms - - - --- 2021-07-01 Matt Roper New
[28/53] drm/i915/dg2: Add SQIDI steering Begin enabling Xe_HP SDV and DG2 platforms - - - --- 2021-07-01 Matt Roper New
[27/53] drm/i915/dg2: Update LNCF steering ranges Begin enabling Xe_HP SDV and DG2 platforms - - - --- 2021-07-01 Matt Roper New
[26/53] drm/i915/dg2: Add forcewake table Begin enabling Xe_HP SDV and DG2 platforms - - - --- 2021-07-01 Matt Roper New
[25/53] drm/i915/dg2: DG2 uses the same sseu limits as XeHP SDV Begin enabling Xe_HP SDV and DG2 platforms - - - --- 2021-07-01 Matt Roper New
[24/53] drm/i915/dg2: add DG2 platform info Begin enabling Xe_HP SDV and DG2 platforms - - - --- 2021-07-01 Matt Roper New
[23/53] drm/i915/xehpsdv: Read correct RP_STATE_CAP register Begin enabling Xe_HP SDV and DG2 platforms - 1 - --- 2021-07-01 Matt Roper New
[22/53] drm/i915/xehpsdv: factor out function to read RP_STATE_CAP Begin enabling Xe_HP SDV and DG2 platforms - - - --- 2021-07-01 Matt Roper New
[21/53] drm/i915/xehpsdv: Define MOCS table for XeHP SDV Begin enabling Xe_HP SDV and DG2 platforms - - - --- 2021-07-01 Matt Roper New
[20/53] drm/i915/xehpsdv: Define steering tables Begin enabling Xe_HP SDV and DG2 platforms - - - --- 2021-07-01 Matt Roper New
[19/53] drm/i915/xehpsdv: Add compute DSS type Begin enabling Xe_HP SDV and DG2 platforms - - - --- 2021-07-01 Matt Roper New
[18/53] drm/i915/xehpsdv: Add maximum sseu limits Begin enabling Xe_HP SDV and DG2 platforms - - - --- 2021-07-01 Matt Roper New
[17/53] drm/i915/xehp: Changes to ss/eu definitions Begin enabling Xe_HP SDV and DG2 platforms - - - --- 2021-07-01 Matt Roper New
[16/53] drm/i915/xehpsdv: add initial XeHP SDV definitions Begin enabling Xe_HP SDV and DG2 platforms - 1 - --- 2021-07-01 Matt Roper New
[15/53] drm/i915/xehp: Loop over all gslices for INSTDONE processing Begin enabling Xe_HP SDV and DG2 platforms - - - --- 2021-07-01 Matt Roper New
[14/53] drm/i915/xehp: handle new steering options Begin enabling Xe_HP SDV and DG2 platforms - - - --- 2021-07-01 Matt Roper New
[13/53] drm/i915/xehp: New engine context offsets Begin enabling Xe_HP SDV and DG2 platforms - - - --- 2021-07-01 Matt Roper New
[12/53] drm/i915/xehp: Handle new device context ID format Begin enabling Xe_HP SDV and DG2 platforms - - - --- 2021-07-01 Matt Roper New
[11/53] drm/i915/xehp: Define multicast register ranges Begin enabling Xe_HP SDV and DG2 platforms - - - --- 2021-07-01 Matt Roper New
[10/53] drm/i915/xehp: Xe_HP forcewake support Begin enabling Xe_HP SDV and DG2 platforms - - - --- 2021-07-01 Matt Roper New
[09/53] drm/i915/xehp: Extra media engines - Part 3 (reset) Begin enabling Xe_HP SDV and DG2 platforms - - - --- 2021-07-01 Matt Roper New
[08/53] drm/i915/xehp: Extra media engines - Part 2 (interrupts) Begin enabling Xe_HP SDV and DG2 platforms - 1 - --- 2021-07-01 Matt Roper New
[07/53] drm/i915/xehp: Extra media engines - Part 1 (engine definitions) Begin enabling Xe_HP SDV and DG2 platforms - - - --- 2021-07-01 Matt Roper New
[06/53] drm/i915/selftests: Allow for larger engine counts Begin enabling Xe_HP SDV and DG2 platforms - 1 - --- 2021-07-01 Matt Roper New
[05/53] drm/i915/gen12: Use fuse info to enable SFC Begin enabling Xe_HP SDV and DG2 platforms - 1 - --- 2021-07-01 Matt Roper New
[04/53] drm/i915/xehp: VDBOX/VEBOX fusing registers are enable-based Begin enabling Xe_HP SDV and DG2 platforms - 1 - --- 2021-07-01 Matt Roper New
[03/53] drm/i915: Fork DG1 interrupt handler Begin enabling Xe_HP SDV and DG2 platforms - - - --- 2021-07-01 Matt Roper New
[02/53] drm/i915: Add XE_HP initial definitions Begin enabling Xe_HP SDV and DG2 platforms - - - --- 2021-07-01 Matt Roper New
[01/53] drm/i915: Add "release id" version Begin enabling Xe_HP SDV and DG2 platforms - - - --- 2021-07-01 Matt Roper New