| Message ID | 0b943c028a05edfd61c511d712c65c7e8bf70211.1540900289.git.jani.nikula@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/icl: dsi enabling | expand |
On 10/30/2018 5:26 PM, Jani Nikula wrote: > From: Madhav Chauhan <madhav.chauhan@intel.com> > > This patch defines DSI_HTX_TO, DSI_LRX_H_TO, DSI_PWAIT_TO > and DSI_TA_TO registers for DSI transcoders '0' and '1'. > They are used for contention recovery on DPHY. > > v2: Define SHIFT for bitfields. > > v3 by Jani: > - Fix timeout bit definitions Ok. I was little confused with BSPEC description "HW will set this bit, SW must clear it with a write of 1b" meaning timeout will happen (reverse behavior) when bit is '0' :). Regards, Madhav > > Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com> > Signed-off-by: Jani Nikula <jani.nikula@intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 43 +++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 43 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index bcee91bcfba6..8d089ef848b2 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -10533,6 +10533,49 @@ enum skl_power_gate { > #define LINK_ULPS_TYPE_LP11 (1 << 8) > #define LINK_ENTER_ULPS (1 << 0) > > +/* DSI timeout registers */ > +#define _DSI_HSTX_TO_0 0x6b044 > +#define _DSI_HSTX_TO_1 0x6b844 > +#define DSI_HSTX_TO(tc) _MMIO_DSI(tc, \ > + _DSI_HSTX_TO_0,\ > + _DSI_HSTX_TO_1) > +#define HSTX_TIMEOUT_VALUE_MASK (0xffff << 16) > +#define HSTX_TIMEOUT_VALUE_SHIFT 16 > +#define HSTX_TIMEOUT_VALUE(x) ((x) << 16) > +#define HSTX_TIMED_OUT (1 << 0) > + > +#define _DSI_LPRX_HOST_TO_0 0x6b048 > +#define _DSI_LPRX_HOST_TO_1 0x6b848 > +#define DSI_LPRX_HOST_TO(tc) _MMIO_DSI(tc, \ > + _DSI_LPRX_HOST_TO_0,\ > + _DSI_LPRX_HOST_TO_1) > +#define LPRX_TIMED_OUT (1 << 16) > +#define LPRX_TIMEOUT_VALUE_MASK (0xffff << 0) > +#define LPRX_TIMEOUT_VALUE_SHIFT 0 > +#define LPRX_TIMEOUT_VALUE(x) ((x) << 0) > + > +#define _DSI_PWAIT_TO_0 0x6b040 > +#define _DSI_PWAIT_TO_1 0x6b840 > +#define DSI_PWAIT_TO(tc) _MMIO_DSI(tc, \ > + _DSI_PWAIT_TO_0,\ > + _DSI_PWAIT_TO_1) > +#define PRESET_TIMEOUT_VALUE_MASK (0xffff << 16) > +#define PRESET_TIMEOUT_VALUE_SHIFT 16 > +#define PRESET_TIMEOUT_VALUE(x) ((x) << 16) > +#define PRESPONSE_TIMEOUT_VALUE_MASK (0xffff << 0) > +#define PRESPONSE_TIMEOUT_VALUE_SHIFT 0 > +#define PRESPONSE_TIMEOUT_VALUE(x) ((x) << 0) > + > +#define _DSI_TA_TO_0 0x6b04c > +#define _DSI_TA_TO_1 0x6b84c > +#define DSI_TA_TO(tc) _MMIO_DSI(tc, \ > + _DSI_TA_TO_0,\ > + _DSI_TA_TO_1) > +#define TA_TIMED_OUT (1 << 16) > +#define TA_TIMEOUT_VALUE_MASK (0xffff << 0) > +#define TA_TIMEOUT_VALUE_SHIFT 0 > +#define TA_TIMEOUT_VALUE(x) ((x) << 0) > + > /* bits 31:0 */ > #define _MIPIA_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb084) > #define _MIPIC_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index bcee91bcfba6..8d089ef848b2 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -10533,6 +10533,49 @@ enum skl_power_gate { #define LINK_ULPS_TYPE_LP11 (1 << 8) #define LINK_ENTER_ULPS (1 << 0) +/* DSI timeout registers */ +#define _DSI_HSTX_TO_0 0x6b044 +#define _DSI_HSTX_TO_1 0x6b844 +#define DSI_HSTX_TO(tc) _MMIO_DSI(tc, \ + _DSI_HSTX_TO_0,\ + _DSI_HSTX_TO_1) +#define HSTX_TIMEOUT_VALUE_MASK (0xffff << 16) +#define HSTX_TIMEOUT_VALUE_SHIFT 16 +#define HSTX_TIMEOUT_VALUE(x) ((x) << 16) +#define HSTX_TIMED_OUT (1 << 0) + +#define _DSI_LPRX_HOST_TO_0 0x6b048 +#define _DSI_LPRX_HOST_TO_1 0x6b848 +#define DSI_LPRX_HOST_TO(tc) _MMIO_DSI(tc, \ + _DSI_LPRX_HOST_TO_0,\ + _DSI_LPRX_HOST_TO_1) +#define LPRX_TIMED_OUT (1 << 16) +#define LPRX_TIMEOUT_VALUE_MASK (0xffff << 0) +#define LPRX_TIMEOUT_VALUE_SHIFT 0 +#define LPRX_TIMEOUT_VALUE(x) ((x) << 0) + +#define _DSI_PWAIT_TO_0 0x6b040 +#define _DSI_PWAIT_TO_1 0x6b840 +#define DSI_PWAIT_TO(tc) _MMIO_DSI(tc, \ + _DSI_PWAIT_TO_0,\ + _DSI_PWAIT_TO_1) +#define PRESET_TIMEOUT_VALUE_MASK (0xffff << 16) +#define PRESET_TIMEOUT_VALUE_SHIFT 16 +#define PRESET_TIMEOUT_VALUE(x) ((x) << 16) +#define PRESPONSE_TIMEOUT_VALUE_MASK (0xffff << 0) +#define PRESPONSE_TIMEOUT_VALUE_SHIFT 0 +#define PRESPONSE_TIMEOUT_VALUE(x) ((x) << 0) + +#define _DSI_TA_TO_0 0x6b04c +#define _DSI_TA_TO_1 0x6b84c +#define DSI_TA_TO(tc) _MMIO_DSI(tc, \ + _DSI_TA_TO_0,\ + _DSI_TA_TO_1) +#define TA_TIMED_OUT (1 << 16) +#define TA_TIMEOUT_VALUE_MASK (0xffff << 0) +#define TA_TIMEOUT_VALUE_SHIFT 0 +#define TA_TIMEOUT_VALUE(x) ((x) << 0) + /* bits 31:0 */ #define _MIPIA_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb084) #define _MIPIC_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884)