diff mbox series

[v8,20/38] drm/i915/icl: Add DSI packet payload/header registers

Message ID 18275c49215e512347a14bc38715314c2d6f95a4.1540900289.git.jani.nikula@intel.com (mailing list archive)
State New, archived
Headers show
Series drm/i915/icl: dsi enabling | expand

Commit Message

Jani Nikula Oct. 30, 2018, 11:56 a.m. UTC 
From: Madhav Chauhan <madhav.chauhan@intel.com>

This patch defines payload/header registers for each DSI
transcoder used for transmitting DSI packets.

v2 by Jani:
 - Drop full register mask and shift for payload
 - Use lower case for hex 0x

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

Comments

Chauhan, Madhav Oct. 31, 2018, 11:43 a.m. UTC | #1 
On 10/30/2018 5:26 PM, Jani Nikula wrote:
> From: Madhav Chauhan <madhav.chauhan@intel.com>
>
> This patch defines payload/header registers for each DSI
> transcoder used for transmitting DSI packets.
>
> v2 by Jani:
>   - Drop full register mask and shift for payload
>   - Use lower case for hex 0x

v2 change are fine.

Regards,
Madhav

>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_reg.h | 22 ++++++++++++++++++++++
>   1 file changed, 22 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8d089ef848b2..639667d0fb00 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -10523,6 +10523,28 @@ enum skl_power_gate {
>   #define  MAX_HEADER_CREDIT		0x10
>   #define  MAX_PLOAD_CREDIT		0x40
>   
> +#define _DSI_CMD_TXHDR_0		0x6b100
> +#define _DSI_CMD_TXHDR_1		0x6b900
> +#define DSI_CMD_TXHDR(tc)		_MMIO_DSI(tc,	\
> +						  _DSI_CMD_TXHDR_0,\
> +						  _DSI_CMD_TXHDR_1)
> +#define  PAYLOAD_PRESENT		(1 << 31)
> +#define  LP_DATA_TRANSFER		(1 << 30)
> +#define  VBLANK_FENCE			(1 << 29)
> +#define  PARAM_WC_MASK			(0xffff << 8)
> +#define  PARAM_WC_LOWER_SHIFT		8
> +#define  PARAM_WC_UPPER_SHIFT		16
> +#define  VC_MASK			(0x3 << 6)
> +#define  VC_SHIFT			6
> +#define  DT_MASK			(0x3f << 0)
> +#define  DT_SHIFT			0
> +
> +#define _DSI_CMD_TXPYLD_0		0x6b104
> +#define _DSI_CMD_TXPYLD_1		0x6b904
> +#define DSI_CMD_TXPYLD(tc)		_MMIO_DSI(tc,	\
> +						  _DSI_CMD_TXPYLD_0,\
> +						  _DSI_CMD_TXPYLD_1)
> +
>   #define _DSI_LP_MSG_0			0x6b0d8
>   #define _DSI_LP_MSG_1			0x6b8d8
>   #define DSI_LP_MSG(tc)			_MMIO_DSI(tc,	\
Jani Nikula Nov. 1, 2018, 11:10 a.m. UTC | #2 
On Wed, 31 Oct 2018, Madhav Chauhan <madhav.chauhan@intel.com> wrote:
> On 10/30/2018 5:26 PM, Jani Nikula wrote:
>> From: Madhav Chauhan <madhav.chauhan@intel.com>
>>
>> This patch defines payload/header registers for each DSI
>> transcoder used for transmitting DSI packets.
>>
>> v2 by Jani:
>>   - Drop full register mask and shift for payload
>>   - Use lower case for hex 0x
>
> v2 change are fine.

Thanks, pushed.

BR,
Jani.

>
> Regards,
> Madhav
>
>>
>> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>>   drivers/gpu/drm/i915/i915_reg.h | 22 ++++++++++++++++++++++
>>   1 file changed, 22 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 8d089ef848b2..639667d0fb00 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -10523,6 +10523,28 @@ enum skl_power_gate {
>>   #define  MAX_HEADER_CREDIT		0x10
>>   #define  MAX_PLOAD_CREDIT		0x40
>>   
>> +#define _DSI_CMD_TXHDR_0		0x6b100
>> +#define _DSI_CMD_TXHDR_1		0x6b900
>> +#define DSI_CMD_TXHDR(tc)		_MMIO_DSI(tc,	\
>> +						  _DSI_CMD_TXHDR_0,\
>> +						  _DSI_CMD_TXHDR_1)
>> +#define  PAYLOAD_PRESENT		(1 << 31)
>> +#define  LP_DATA_TRANSFER		(1 << 30)
>> +#define  VBLANK_FENCE			(1 << 29)
>> +#define  PARAM_WC_MASK			(0xffff << 8)
>> +#define  PARAM_WC_LOWER_SHIFT		8
>> +#define  PARAM_WC_UPPER_SHIFT		16
>> +#define  VC_MASK			(0x3 << 6)
>> +#define  VC_SHIFT			6
>> +#define  DT_MASK			(0x3f << 0)
>> +#define  DT_SHIFT			0
>> +
>> +#define _DSI_CMD_TXPYLD_0		0x6b104
>> +#define _DSI_CMD_TXPYLD_1		0x6b904
>> +#define DSI_CMD_TXPYLD(tc)		_MMIO_DSI(tc,	\
>> +						  _DSI_CMD_TXPYLD_0,\
>> +						  _DSI_CMD_TXPYLD_1)
>> +
>>   #define _DSI_LP_MSG_0			0x6b0d8
>>   #define _DSI_LP_MSG_1			0x6b8d8
>>   #define DSI_LP_MSG(tc)			_MMIO_DSI(tc,	\
>
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8d089ef848b2..639667d0fb00 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10523,6 +10523,28 @@  enum skl_power_gate {
 #define  MAX_HEADER_CREDIT		0x10
 #define  MAX_PLOAD_CREDIT		0x40
 
+#define _DSI_CMD_TXHDR_0		0x6b100
+#define _DSI_CMD_TXHDR_1		0x6b900
+#define DSI_CMD_TXHDR(tc)		_MMIO_DSI(tc,	\
+						  _DSI_CMD_TXHDR_0,\
+						  _DSI_CMD_TXHDR_1)
+#define  PAYLOAD_PRESENT		(1 << 31)
+#define  LP_DATA_TRANSFER		(1 << 30)
+#define  VBLANK_FENCE			(1 << 29)
+#define  PARAM_WC_MASK			(0xffff << 8)
+#define  PARAM_WC_LOWER_SHIFT		8
+#define  PARAM_WC_UPPER_SHIFT		16
+#define  VC_MASK			(0x3 << 6)
+#define  VC_SHIFT			6
+#define  DT_MASK			(0x3f << 0)
+#define  DT_SHIFT			0
+
+#define _DSI_CMD_TXPYLD_0		0x6b104
+#define _DSI_CMD_TXPYLD_1		0x6b904
+#define DSI_CMD_TXPYLD(tc)		_MMIO_DSI(tc,	\
+						  _DSI_CMD_TXPYLD_0,\
+						  _DSI_CMD_TXPYLD_1)
+
 #define _DSI_LP_MSG_0			0x6b0d8
 #define _DSI_LP_MSG_1			0x6b8d8
 #define DSI_LP_MSG(tc)			_MMIO_DSI(tc,	\