| Message ID | 1351723265-4086-4-git-send-email-jbarnes@virtuousgeek.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Wed, 31 Oct 2012 15:41:05 -0700, Jesse Barnes <jbarnes@virtuousgeek.org> wrote: > The BIOS shouldn't be touching this memory across suspend/resume, so > just leave it alone. This saves us ~6ms on resume on my T420 (retested > with write combined PTEs). > > v2: change gtt restore default on pre-gen4 (Chris) > move needs_gtt_restore flag into dev_priv > v3: make sure we restore GTT on resume from hibernate (Daniel) > use opregion support as the cutoff for restore from resume (Chris) > > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> My troublesome PNV of yore remains happy with this patch, so Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Bikeshed: intel_bios_has_opregion(), as we test for this in different locations in different ways. -Chris
On Fri, 02 Nov 2012 15:16:36 +0000 Chris Wilson <chris@chris-wilson.co.uk> wrote: > On Wed, 31 Oct 2012 15:41:05 -0700, Jesse Barnes <jbarnes@virtuousgeek.org> wrote: > > The BIOS shouldn't be touching this memory across suspend/resume, so > > just leave it alone. This saves us ~6ms on resume on my T420 (retested > > with write combined PTEs). > > > > v2: change gtt restore default on pre-gen4 (Chris) > > move needs_gtt_restore flag into dev_priv > > v3: make sure we restore GTT on resume from hibernate (Daniel) > > use opregion support as the cutoff for restore from resume (Chris) > > > > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> > > My troublesome PNV of yore remains happy with this patch, so > Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> > > Bikeshed: intel_bios_has_opregion(), as we test for this in different > locations in different ways. > -Chris > Ended up using dev_priv->opregion.header as the check, seems simplier. Integrated your other comments and reposted a new series.
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index 1ce7e49..69ac4a5 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c @@ -1467,6 +1467,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) struct intel_device_info *info; int ret = 0, mmio_bar, mmio_size; uint32_t aperture_size; + bool opregion_supported = false; info = (struct intel_device_info *) flags; @@ -1592,7 +1593,12 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) /* Try to make sure MCHBAR is enabled before poking at it */ intel_setup_mchbar(dev); intel_setup_gmbus(dev); - intel_opregion_setup(dev); + if (!intel_opregion_setup(dev)) + opregion_supported = true; + + /* Gen3+ should have saner BIOSes (we hope) */ + if (!opregion_supported) + dev_priv->needs_gtt_restore = true; /* Make sure the bios did its job and set up vital registers */ intel_setup_bios(dev); diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 9feedb4..1ea70ec 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -533,19 +533,11 @@ void intel_console_resume(struct work_struct *work) console_unlock(); } -static int i915_drm_thaw(struct drm_device *dev) +static int __i915_drm_thaw(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; int error = 0; - intel_gt_reset(dev); - - if (drm_core_check_feature(dev, DRIVER_MODESET)) { - mutex_lock(&dev->struct_mutex); - i915_gem_restore_gtt_mappings(dev); - mutex_unlock(&dev->struct_mutex); - } - i915_restore_state(dev); intel_opregion_setup(dev); @@ -574,8 +566,26 @@ static int i915_drm_thaw(struct drm_device *dev) return error; } +static int i915_drm_thaw(struct drm_device *dev) +{ + int error = 0; + + intel_gt_reset(dev); + + if (drm_core_check_feature(dev, DRIVER_MODESET)) { + mutex_lock(&dev->struct_mutex); + i915_gem_restore_gtt_mappings(dev); + mutex_unlock(&dev->struct_mutex); + } + + __i915_drm_thaw(dev); + + return error; +} + int i915_resume(struct drm_device *dev) { + struct drm_i915_private *dev_priv = dev->dev_private; int ret; if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) @@ -586,7 +596,16 @@ int i915_resume(struct drm_device *dev) pci_set_master(dev->pdev); - ret = i915_drm_thaw(dev); + intel_gt_reset(dev); + + if (drm_core_check_feature(dev, DRIVER_MODESET) && + dev_priv->needs_gtt_restore) { + mutex_lock(&dev->struct_mutex); + i915_gem_restore_gtt_mappings(dev); + mutex_unlock(&dev->struct_mutex); + } + + ret = __i915_drm_thaw(dev); if (ret) return ret; diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index b41a90b..df65e48 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -881,6 +881,8 @@ typedef struct drm_i915_private { struct delayed_work gen6_power_work; + bool needs_gtt_restore; + enum no_fbc_reason no_fbc_reason; struct drm_mm_node *compressed_fb;
The BIOS shouldn't be touching this memory across suspend/resume, so just leave it alone. This saves us ~6ms on resume on my T420 (retested with write combined PTEs). v2: change gtt restore default on pre-gen4 (Chris) move needs_gtt_restore flag into dev_priv v3: make sure we restore GTT on resume from hibernate (Daniel) use opregion support as the cutoff for restore from resume (Chris) Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> --- drivers/gpu/drm/i915/i915_dma.c | 8 +++++++- drivers/gpu/drm/i915/i915_drv.c | 39 +++++++++++++++++++++++++++++---------- drivers/gpu/drm/i915/i915_drv.h | 2 ++ 3 files changed, 38 insertions(+), 11 deletions(-)