@@ -344,11 +344,14 @@ void i915_gem_init_ppgtt(struct drm_device *dev)
}
for_each_ring(ring, dev_priv, i) {
+ /* Directory CacheLine Valid controls which PDEs are held in the
+ * directory cache. Each bit represents 16 PDEs */
+ uint64_t dclv = ppgtt->mapped_size >> 26;
+ dclv = (1ULL << dclv) - 1;
if (INTEL_INFO(dev)->gen >= 7)
I915_WRITE(RING_MODE_GEN7(ring),
_MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
-
- I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
+ I915_WRITE(RING_PP_DIR_DCLV(ring), dclv);
I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset);
}
}
@@ -117,7 +117,6 @@
#define RING_PP_DIR_BASE(ring) ((ring)->mmio_base+0x228)
#define RING_PP_DIR_BASE_READ(ring) ((ring)->mmio_base+0x518)
#define RING_PP_DIR_DCLV(ring) ((ring)->mmio_base+0x220)
-#define PP_DIR_DCLV_2G 0xffffffff
#define GAM_ECOCHK 0x4090
#define ECOCHK_SNB_BIT (1<<10)