| Message ID | 1373373867-28080-1-git-send-email-daniel.vetter@ffwll.ch (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Tue, Jul 09, 2013 at 02:44:26PM +0200, Daniel Vetter wrote: > Originally I've thought that this fixes up the reset issues on my > gm45, but that was just a red herring due to b0rked testing. > > Still I much prefer writing the right values (all other fields are > reserved) instead of potentially dragging gunk around. Hence also > clear the register to 0 after a reset. > > Note that Cspec is a bit confused and doesn't explicitly say that all > the other bits in this register are "reserved, mbz" like usually. > Instead they're marked as "r/o, default value = 0" which semantically > amounts to the same thing. > > v2: Stop claiming this fixes anything and return 0 if successful > instead of stack garbage. > > v3: Pimp the commit message to explain exactly why I think the docs > allow us to ditch the rmw cycle, spurred by a discussion with Chris. > > Cc: Chris Wilson <chris@chris-wilson.co.uk> > Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Bugzilla? Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> -Chris
On Tue, Jul 09, 2013 at 02:56:01PM +0100, Chris Wilson wrote: > On Tue, Jul 09, 2013 at 02:44:26PM +0200, Daniel Vetter wrote: > > Originally I've thought that this fixes up the reset issues on my > > gm45, but that was just a red herring due to b0rked testing. > > > > Still I much prefer writing the right values (all other fields are > > reserved) instead of potentially dragging gunk around. Hence also > > clear the register to 0 after a reset. > > > > Note that Cspec is a bit confused and doesn't explicitly say that all > > the other bits in this register are "reserved, mbz" like usually. > > Instead they're marked as "r/o, default value = 0" which semantically > > amounts to the same thing. > > > > v2: Stop claiming this fixes anything and return 0 if successful > > instead of stack garbage. > > > > v3: Pimp the commit message to explain exactly why I think the docs > > allow us to ditch the rmw cycle, spurred by a discussion with Chris. > > > > Cc: Chris Wilson <chris@chris-wilson.co.uk> > > Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> > Bugzilla? I've dropped the bugzilla ref since at most this is Inspired-by: which is a bit a useless tag. The bug itself was the lack of hw status page reinit, which is clearly a completely different issue. > Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Queued for -next, thanks for the review. -Daniel
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index e6dc81c..5400d2b 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -798,28 +798,29 @@ static int i965_reset_complete(struct drm_device *dev) static int i965_do_reset(struct drm_device *dev) { int ret; - u8 gdrst; /* * Set the domains we want to reset (GRDOM/bits 2 and 3) as * well as the reset bit (GR/bit 0). Setting the GR bit * triggers the reset; when done, the hardware will clear it. */ - pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst); pci_write_config_byte(dev->pdev, I965_GDRST, - gdrst | GRDOM_RENDER | - GRDOM_RESET_ENABLE); + GRDOM_RENDER | GRDOM_RESET_ENABLE); ret = wait_for(i965_reset_complete(dev), 500); if (ret) return ret; /* We can't reset render&media without also resetting display ... */ - pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst); pci_write_config_byte(dev->pdev, I965_GDRST, - gdrst | GRDOM_MEDIA | - GRDOM_RESET_ENABLE); + GRDOM_MEDIA | GRDOM_RESET_ENABLE); - return wait_for(i965_reset_complete(dev), 500); + ret = wait_for(i965_reset_complete(dev), 500); + if (ret) + return ret; + + pci_write_config_byte(dev->pdev, I965_GDRST, 0); + + return 0; } static int ironlake_do_reset(struct drm_device *dev)
Originally I've thought that this fixes up the reset issues on my gm45, but that was just a red herring due to b0rked testing. Still I much prefer writing the right values (all other fields are reserved) instead of potentially dragging gunk around. Hence also clear the register to 0 after a reset. Note that Cspec is a bit confused and doesn't explicitly say that all the other bits in this register are "reserved, mbz" like usually. Instead they're marked as "r/o, default value = 0" which semantically amounts to the same thing. v2: Stop claiming this fixes anything and return 0 if successful instead of stack garbage. v3: Pimp the commit message to explain exactly why I think the docs allow us to ditch the rmw cycle, spurred by a discussion with Chris. Cc: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> --- drivers/gpu/drm/i915/i915_drv.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-)