diff mbox

[5/5] drm/i915/bdw: Add support for DRRS to switch RR

Message ID 1387785153-5329-6-git-send-email-vandana.kannan@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

vandana.kannan@intel.com Dec. 23, 2013, 7:52 a.m. UTC 
For Broadwell, there is one instance of Transcoder MN values per transcoder.
For dynamic switching between multiple refreshr rates, M/N values may be
reprogrammed on the fly. Link N programming triggers update of all data and
link M & N registers and the new M/N values will be used in the next frame
that is output.

v2: Incorporated Chris's review comments
Changed to check for gen >=8 or gen > 5 before setting M/N registers

Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
Signed-off-by: Pradeep Bhat <pradeep.bhat@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c |   32 +++++++++++++++++++++++++-------
 1 file changed, 25 insertions(+), 7 deletions(-)

Comments

Jani Nikula Jan. 22, 2014, 2:34 p.m. UTC | #1 
On Mon, 23 Dec 2013, Vandana Kannan <vandana.kannan@intel.com> wrote:
> For Broadwell, there is one instance of Transcoder MN values per transcoder.
> For dynamic switching between multiple refreshr rates, M/N values may be
> reprogrammed on the fly. Link N programming triggers update of all data and
> link M & N registers and the new M/N values will be used in the next frame
> that is output.
>
> v2: Incorporated Chris's review comments
> Changed to check for gen >=8 or gen > 5 before setting M/N registers
>
> Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
> Signed-off-by: Pradeep Bhat <pradeep.bhat@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp.c |   32 +++++++++++++++++++++++++-------
>  1 file changed, 25 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 7778808..f18a585 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -798,11 +798,20 @@ intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n)
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	enum transcoder transcoder = crtc->config.cpu_transcoder;
>  
> -	I915_WRITE(PIPE_DATA_M2(transcoder),
> -		TU_SIZE(m_n->tu) | m_n->gmch_m);
> -	I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n);
> -	I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m);
> -	I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n);
> +	if (INTEL_INFO(dev)->gen >= 8) {
> +		I915_WRITE(PIPE_DATA_M1(transcoder),
> +			TU_SIZE(m_n->tu) | m_n->gmch_m);
> +		I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
> +		I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
> +		I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);

There's already a function for this part, called
intel_cpu_transcoder_set_m_n. Reuse it.

> +	} else if (INTEL_INFO(dev)->gen >= 5) {
> +		I915_WRITE(PIPE_DATA_M2(transcoder),
> +			TU_SIZE(m_n->tu) | m_n->gmch_m);
> +		I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n);
> +		I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m);
> +		I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n);
> +	}
> +
>  	return;
>  }
>  
> @@ -3612,8 +3621,17 @@ intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate) {
>  
>  	mutex_lock(&intel_dp->drrs_state.mutex);
>  
> -	/* Haswell and below */

Forgot to mention in the earlier patch that comments like this are
redundant with the code. And in this case, it already *contradicts* the
code.

> -	if (INTEL_INFO(dev)->gen >= 5 && INTEL_INFO(dev)->gen < 8) {
> +	if (INTEL_INFO(dev)->gen >= 8) {
> +		switch (index) {
> +		case DRRS_HIGH_RR:
> +			intel_dp_set_m2_n2(intel_crtc, &config->dp_m_n);
> +			break;
> +		case DRRS_LOW_RR:
> +			intel_dp_set_m2_n2(intel_crtc, &config->dp_m2_n2);
> +			break;
> +		};
> +	} else if (INTEL_INFO(dev)->gen >= 5) {
> +		/* Haswell and below */
>  		reg = PIPECONF(intel_crtc->config.cpu_transcoder);
>  		val = I915_READ(reg);
>  		if (index > DRRS_HIGH_RR) {
> -- 
> 1.7.9.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
vandana.kannan@intel.com Jan. 30, 2014, 3:52 a.m. UTC | #2 
On Jan-22-2014 8:04 PM, Jani Nikula wrote:
> On Mon, 23 Dec 2013, Vandana Kannan <vandana.kannan@intel.com> wrote:
>> For Broadwell, there is one instance of Transcoder MN values per transcoder.
>> For dynamic switching between multiple refreshr rates, M/N values may be
>> reprogrammed on the fly. Link N programming triggers update of all data and
>> link M & N registers and the new M/N values will be used in the next frame
>> that is output.
>>
>> v2: Incorporated Chris's review comments
>> Changed to check for gen >=8 or gen > 5 before setting M/N registers
>>
>> Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
>> Signed-off-by: Pradeep Bhat <pradeep.bhat@intel.com>
>> ---
>>  drivers/gpu/drm/i915/intel_dp.c |   32 +++++++++++++++++++++++++-------
>>  1 file changed, 25 insertions(+), 7 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>> index 7778808..f18a585 100644
>> --- a/drivers/gpu/drm/i915/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>> @@ -798,11 +798,20 @@ intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n)
>>  	struct drm_i915_private *dev_priv = dev->dev_private;
>>  	enum transcoder transcoder = crtc->config.cpu_transcoder;
>>  
>> -	I915_WRITE(PIPE_DATA_M2(transcoder),
>> -		TU_SIZE(m_n->tu) | m_n->gmch_m);
>> -	I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n);
>> -	I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m);
>> -	I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n);
>> +	if (INTEL_INFO(dev)->gen >= 8) {
>> +		I915_WRITE(PIPE_DATA_M1(transcoder),
>> +			TU_SIZE(m_n->tu) | m_n->gmch_m);
>> +		I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
>> +		I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
>> +		I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
> 
> There's already a function for this part, called
> intel_cpu_transcoder_set_m_n. Reuse it.
> 
Ok. I will make necessary changes
>> +	} else if (INTEL_INFO(dev)->gen >= 5) {
>> +		I915_WRITE(PIPE_DATA_M2(transcoder),
>> +			TU_SIZE(m_n->tu) | m_n->gmch_m);
>> +		I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n);
>> +		I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m);
>> +		I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n);
>> +	}
>> +
>>  	return;
>>  }
>>  
>> @@ -3612,8 +3621,17 @@ intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate) {
>>  
>>  	mutex_lock(&intel_dp->drrs_state.mutex);
>>  
>> -	/* Haswell and below */
> 
> Forgot to mention in the earlier patch that comments like this are
> redundant with the code. And in this case, it already *contradicts* the
> code.
> 
>> -	if (INTEL_INFO(dev)->gen >= 5 && INTEL_INFO(dev)->gen < 8) {
>> +	if (INTEL_INFO(dev)->gen >= 8) {
>> +		switch (index) {
>> +		case DRRS_HIGH_RR:
>> +			intel_dp_set_m2_n2(intel_crtc, &config->dp_m_n);
>> +			break;
>> +		case DRRS_LOW_RR:
>> +			intel_dp_set_m2_n2(intel_crtc, &config->dp_m2_n2);
>> +			break;
>> +		};
>> +	} else if (INTEL_INFO(dev)->gen >= 5) {
>> +		/* Haswell and below */
This comment can be removed.
>>  		reg = PIPECONF(intel_crtc->config.cpu_transcoder);
>>  		val = I915_READ(reg);
>>  		if (index > DRRS_HIGH_RR) {
>> -- 
>> 1.7.9.5
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 7778808..f18a585 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -798,11 +798,20 @@  intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	enum transcoder transcoder = crtc->config.cpu_transcoder;
 
-	I915_WRITE(PIPE_DATA_M2(transcoder),
-		TU_SIZE(m_n->tu) | m_n->gmch_m);
-	I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n);
-	I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m);
-	I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n);
+	if (INTEL_INFO(dev)->gen >= 8) {
+		I915_WRITE(PIPE_DATA_M1(transcoder),
+			TU_SIZE(m_n->tu) | m_n->gmch_m);
+		I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
+		I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
+		I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
+	} else if (INTEL_INFO(dev)->gen >= 5) {
+		I915_WRITE(PIPE_DATA_M2(transcoder),
+			TU_SIZE(m_n->tu) | m_n->gmch_m);
+		I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n);
+		I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m);
+		I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n);
+	}
+
 	return;
 }
 
@@ -3612,8 +3621,17 @@  intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate) {
 
 	mutex_lock(&intel_dp->drrs_state.mutex);
 
-	/* Haswell and below */
-	if (INTEL_INFO(dev)->gen >= 5 && INTEL_INFO(dev)->gen < 8) {
+	if (INTEL_INFO(dev)->gen >= 8) {
+		switch (index) {
+		case DRRS_HIGH_RR:
+			intel_dp_set_m2_n2(intel_crtc, &config->dp_m_n);
+			break;
+		case DRRS_LOW_RR:
+			intel_dp_set_m2_n2(intel_crtc, &config->dp_m2_n2);
+			break;
+		};
+	} else if (INTEL_INFO(dev)->gen >= 5) {
+		/* Haswell and below */
 		reg = PIPECONF(intel_crtc->config.cpu_transcoder);
 		val = I915_READ(reg);
 		if (index > DRRS_HIGH_RR) {