| Message ID | 1395981902-21606-7-git-send-email-vandana.kannan@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Fri, 28 Mar 2014, Vandana Kannan <vandana.kannan@intel.com> wrote: > Definition of VLV RR switch bit and corresponding toggling in > set_drrs function. Reviewed-by: Jani Nikula <jani.nikula@intel.com> > Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> > Signed-off-by: Uma Shankar <uma.shankar@intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 1 + > drivers/gpu/drm/i915/intel_dp.c | 10 ++++++++-- > 2 files changed, 9 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 04fc64a..435ed64 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -3257,6 +3257,7 @@ enum punit_power_well { > #define PIPECONF_INTERLACE_MODE_MASK (7 << 21) > #define PIPECONF_EDP_RR_MODE_SWITCH (1 << 20) > #define PIPECONF_CXSR_DOWNCLOCK (1<<16) > +#define PIPECONF_EDP_RR_MODE_SWITCH_VLV (1 << 14) > #define PIPECONF_COLOR_RANGE_SELECT (1 << 13) > #define PIPECONF_BPC_MASK (0x7 << 5) > #define PIPECONF_8BPC (0<<5) > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > index 6cdbb38..79d880b 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -3721,10 +3721,16 @@ void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate) > reg = PIPECONF(intel_crtc->config.cpu_transcoder); > val = I915_READ(reg); > if (index > DRRS_HIGH_RR) { > - val |= PIPECONF_EDP_RR_MODE_SWITCH; > + if (IS_VALLEYVIEW(dev)) > + val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV; > + else > + val |= PIPECONF_EDP_RR_MODE_SWITCH; > intel_dp_set_m2_n2(intel_crtc, &config->dp_m2_n2); > } else { > - val &= ~PIPECONF_EDP_RR_MODE_SWITCH; > + if (IS_VALLEYVIEW(dev)) > + val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV; > + else > + val &= ~PIPECONF_EDP_RR_MODE_SWITCH; > } > I915_WRITE(reg, val); > } > -- > 1.7.9.5 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 04fc64a..435ed64 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3257,6 +3257,7 @@ enum punit_power_well { #define PIPECONF_INTERLACE_MODE_MASK (7 << 21) #define PIPECONF_EDP_RR_MODE_SWITCH (1 << 20) #define PIPECONF_CXSR_DOWNCLOCK (1<<16) +#define PIPECONF_EDP_RR_MODE_SWITCH_VLV (1 << 14) #define PIPECONF_COLOR_RANGE_SELECT (1 << 13) #define PIPECONF_BPC_MASK (0x7 << 5) #define PIPECONF_8BPC (0<<5) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 6cdbb38..79d880b 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -3721,10 +3721,16 @@ void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate) reg = PIPECONF(intel_crtc->config.cpu_transcoder); val = I915_READ(reg); if (index > DRRS_HIGH_RR) { - val |= PIPECONF_EDP_RR_MODE_SWITCH; + if (IS_VALLEYVIEW(dev)) + val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV; + else + val |= PIPECONF_EDP_RR_MODE_SWITCH; intel_dp_set_m2_n2(intel_crtc, &config->dp_m2_n2); } else { - val &= ~PIPECONF_EDP_RR_MODE_SWITCH; + if (IS_VALLEYVIEW(dev)) + val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV; + else + val &= ~PIPECONF_EDP_RR_MODE_SWITCH; } I915_WRITE(reg, val); }