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[7/7] drm/i915: Enable eDP DRRS for CHV

Message ID 1418916741-31452-8-git-send-email-vandana.kannan@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

vandana.kannan@intel.com Dec. 18, 2014, 3:32 p.m. UTC 
From: Durgadoss R <durgadoss.r@intel.com>

This patch enables eDP DRRS for CHV by adding the
required IS_CHERRYVIEW() checks.
CHV uses the same register bit as VLV.

[Vandana]: Since CHV has 2 sets of M_N registers, it will follow the same code
path as gen < 8. Added CHV check in dp_set_m_n()

Signed-off-by: Durgadoss R <durgadoss.r@intel.com>
Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 4 ++--
 drivers/gpu/drm/i915/intel_dp.c      | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

Comments

Shuang He Dec. 19, 2014, 9:42 a.m. UTC | #1 
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                 -1              364/364              363/364
ILK              +1-7              362/364              356/364
SNB                 -1              448/450              447/450
IVB                 -1              497/498              496/498
BYT                 -1              289/289              288/289
HSW                 -2              557/558              555/558
BDW                 -1              416/417              415/417
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
 PNV  igt_gem_exec_blt      NRUN(4, M23M7M25)PASS(1, M25)      NRUN(1, M25)
 ILK  igt_gem_exec_blt      NRUN(7, M37M26)PASS(1, M26)      NRUN(1, M26)
 ILK  igt_kms_render_direct-render      DMESG_WARN(1, M26)PASS(3, M26)      DMESG_WARN(1, M26)
 ILK  igt_kms_flip_bcs-flip-vs-modeset-interruptible      DMESG_WARN(1, M26)PASS(10, M37M26)      PASS(1, M26)
*ILK  igt_kms_flip_blocking-absolute-wf_vblank-interruptible      DMESG_WARN(1, M26)PASS(2, M26)      NSPT(1, M26)
*ILK  igt_kms_flip_busy-flip-interruptible      PASS(3, M26)      DMESG_WARN(1, M26)
*ILK  igt_kms_flip_rcs-flip-vs-dpms      NSPT(1, M26)PASS(3, M26)      DMESG_WARN(1, M26)
*ILK  igt_kms_flip_rcs-flip-vs-panning      PASS(2, M26)      DMESG_WARN(1, M26)
*ILK  igt_kms_flip_vblank-vs-hang      PASS(3, M26)      DMESG_WARN(1, M26)
 SNB  igt_gem_exec_blt      NRUN(7, M35M22)PASS(1, M35)      NRUN(1, M35)
 IVB  igt_gem_exec_blt      NRUN(7, M34M21M4)PASS(1, M34)      NRUN(1, M34)
 BYT  igt_gem_exec_blt      NRUN(7, M48M49M50M51)PASS(1, M48)      NRUN(1, M48)
 HSW  igt_gem_exec_blt      NRUN(7, M40M20M19)PASS(1, M40)      NRUN(1, M19)
*HSW  igt_kms_flip_plain-flip-ts-check      PASS(2, M40M19)      INIT(1, M19)
 BDW  igt_gem_exec_blt      NRUN(6, M30M28)PASS(1, M28)      NRUN(1, M28)
Note: You need to pay more attention to line start with '*'
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 0239681..06bfbbb 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5810,8 +5810,8 @@  void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
 		 * for gen < 8) and if DRRS is supported (to make sure the
 		 * registers are not unnecessarily accessed).
 		 */
-		if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
-			crtc->config.has_drrs) {
+		if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8)
+			&& crtc->config.has_drrs) {
 			I915_WRITE(PIPE_DATA_M2(transcoder),
 					TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
 			I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index ef8fa94..092ef91 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4802,7 +4802,7 @@  static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
 		return;
 	}
 
-	if (INTEL_INFO(dev)->gen >= 8) {
+	if (INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev)) {
 		switch(index) {
 		case DRRS_HIGH_RR:
 			intel_dp_set_m_n(intel_crtc);