| Message ID | 1430379455-21244-3-git-send-email-vandana.kannan@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On to, 2015-04-30 at 13:07 +0530, Vandana Kannan wrote: > Second set of PPS registers have been defined but will be used when VBT > provides a selection between the 2 sets of registers. > > Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> > Signed-off-by: A.Sunil Kamath <sunil.kamath@intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 580f5cb..199a1747 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -6345,6 +6345,12 @@ enum skl_disp_power_wells { > #define PANEL_POWER_CYCLE_DELAY_MASK (0x1f) > #define PANEL_POWER_CYCLE_DELAY_SHIFT 0 > > +/* BXT PPS changes - 2nd set of PPS registers */ > +#define BXT_PP_STATUS2 0xc7300 > +#define BXT_PP_CONTROL2 0xc7304 > +#define BXT_PP_ON_DELAYS2 0xc7308 > +#define BXT_PP_OFF_DELAYS2 0xc730c > + Can we add these in the (future) patch which takes them into use? > #define PCH_DP_B 0xe4100 > #define PCH_DPB_AUX_CH_CTL 0xe4110 > #define PCH_DPB_AUX_CH_DATA1 0xe4114
On Thu, 30 Apr 2015, Imre Deak <imre.deak@intel.com> wrote: > On to, 2015-04-30 at 13:07 +0530, Vandana Kannan wrote: >> Second set of PPS registers have been defined but will be used when VBT >> provides a selection between the 2 sets of registers. >> >> Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> >> Signed-off-by: A.Sunil Kamath <sunil.kamath@intel.com> >> --- >> drivers/gpu/drm/i915/i915_reg.h | 6 ++++++ >> 1 file changed, 6 insertions(+) >> >> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h >> index 580f5cb..199a1747 100644 >> --- a/drivers/gpu/drm/i915/i915_reg.h >> +++ b/drivers/gpu/drm/i915/i915_reg.h >> @@ -6345,6 +6345,12 @@ enum skl_disp_power_wells { >> #define PANEL_POWER_CYCLE_DELAY_MASK (0x1f) >> #define PANEL_POWER_CYCLE_DELAY_SHIFT 0 >> >> +/* BXT PPS changes - 2nd set of PPS registers */ >> +#define BXT_PP_STATUS2 0xc7300 >> +#define BXT_PP_CONTROL2 0xc7304 >> +#define BXT_PP_ON_DELAYS2 0xc7308 >> +#define BXT_PP_OFF_DELAYS2 0xc730c >> + > > Can we add these in the (future) patch which takes them into use? See my review comment, we should use them off the bat. BR, Jani. > >> #define PCH_DP_B 0xe4100 >> #define PCH_DPB_AUX_CH_CTL 0xe4110 >> #define PCH_DPB_AUX_CH_DATA1 0xe4114 > > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 6296
-------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied
PNV 276/276 276/276
ILK 302/302 302/302
SNB 316/316 316/316
IVB 264/264 264/264
BYT -4 227/227 223/227
BDW 318/318 318/318
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
*BYT igt@drm_vma_limiter_cached FAIL(4)PASS(3) FAIL(1)NO_RESULT(1)
*BYT igt@gem_dummy_reloc_loop@render FAIL(1)PASS(15) TIMEOUT(1)PASS(1)
BYT igt@gem_pipe_control_store_loop@fresh-buffer FAIL(1)TIMEOUT(7)PASS(9) TIMEOUT(1)PASS(1)
*BYT igt@gem_tiled_pread FAIL(1)PASS(4) DMESG_WARN(1)PASS(1)
(dmesg patch applied)drm:check_crtc_state[i915]]*ERROR*mismatch_in_has_infoframe(expected#,found#)@mismatch in has_infoframe .* found
WARNING:at_drivers/gpu/drm/i915/intel_display.c:#check_crtc_state[i915]()@WARNING:.* at .* check_crtc_state+0x
Note: You need to pay more attention to line start with '*'
On 4/30/2015 4:53 PM, Jani Nikula wrote: > On Thu, 30 Apr 2015, Imre Deak <imre.deak@intel.com> wrote: >> On to, 2015-04-30 at 13:07 +0530, Vandana Kannan wrote: >>> Second set of PPS registers have been defined but will be used when VBT >>> provides a selection between the 2 sets of registers. >>> >>> Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> >>> Signed-off-by: A.Sunil Kamath <sunil.kamath@intel.com> >>> --- >>> drivers/gpu/drm/i915/i915_reg.h | 6 ++++++ >>> 1 file changed, 6 insertions(+) >>> >>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h >>> index 580f5cb..199a1747 100644 >>> --- a/drivers/gpu/drm/i915/i915_reg.h >>> +++ b/drivers/gpu/drm/i915/i915_reg.h >>> @@ -6345,6 +6345,12 @@ enum skl_disp_power_wells { >>> #define PANEL_POWER_CYCLE_DELAY_MASK (0x1f) >>> #define PANEL_POWER_CYCLE_DELAY_SHIFT 0 >>> >>> +/* BXT PPS changes - 2nd set of PPS registers */ >>> +#define BXT_PP_STATUS2 0xc7300 >>> +#define BXT_PP_CONTROL2 0xc7304 >>> +#define BXT_PP_ON_DELAYS2 0xc7308 >>> +#define BXT_PP_OFF_DELAYS2 0xc730c >>> + >> >> Can we add these in the (future) patch which takes them into use? > > See my review comment, we should use them off the bat. > > BR, > Jani. > Agree with all your review comments. I've made the changes and will be resending the patch today. - Vandana >> >>> #define PCH_DP_B 0xe4100 >>> #define PCH_DPB_AUX_CH_CTL 0xe4110 >>> #define PCH_DPB_AUX_CH_DATA1 0xe4114 >> >> >> _______________________________________________ >> Intel-gfx mailing list >> Intel-gfx@lists.freedesktop.org >> http://lists.freedesktop.org/mailman/listinfo/intel-gfx >
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 580f5cb..199a1747 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6345,6 +6345,12 @@ enum skl_disp_power_wells { #define PANEL_POWER_CYCLE_DELAY_MASK (0x1f) #define PANEL_POWER_CYCLE_DELAY_SHIFT 0 +/* BXT PPS changes - 2nd set of PPS registers */ +#define BXT_PP_STATUS2 0xc7300 +#define BXT_PP_CONTROL2 0xc7304 +#define BXT_PP_ON_DELAYS2 0xc7308 +#define BXT_PP_OFF_DELAYS2 0xc730c + #define PCH_DP_B 0xe4100 #define PCH_DPB_AUX_CH_CTL 0xe4110 #define PCH_DPB_AUX_CH_DATA1 0xe4114