| Message ID | 1443188026-1222-6-git-send-email-arun.siluvery@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Fri, Sep 25, 2015 at 02:33:39PM +0100, Arun Siluvery wrote: > The implementation for this WA is same as WaSetHdcUnitClockGatingDisableInUcgctl6. > Both of them are for BXT:A0 except that WaSetHdcUnitClockGatingDisableInUcgctl6 > is applicable only when either SS0 or SS2 is active but if we apply the former WA > then the latter one also gets applied irrespective of which SS is enabled. > > Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com> > --- > drivers/gpu/drm/i915/intel_pm.c | 15 ++++++++++----- > 1 file changed, 10 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 093a5e4..c73d37d 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -124,12 +124,17 @@ static void bxt_init_clock_gating(struct drm_device *dev) > I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | > GEN8_SDEUNIT_CLOCK_GATE_DISABLE); > > - /* > - * FIXME: > - * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only. > + /* WaSetHDCunitClckGatingDisable:bxt */ > + /* WaSetHdcUnitClockGatingDisableInUcgctl6:bxt */ > + /* The implementation is same for both of these WA except that > + * WaSetHdcUnitClockGatingDisableInUcgctl6 is only applicable when > + * either SS0 or SS2 is active but if we apply the first one then the > + * second one also gets applied irrespective of which SS is enabled. > */ > - I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | > - GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ); > + if (INTEL_REVID(dev) == BXT_REVID_A0) { > + I915_WRITE(GEN8_UCGCTL6, (I915_READ(GEN8_UCGCTL6) | > + GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ)); > + } Again BSpec seems confused. It says this applies to BXT from A0, and SKL from C0. The register description only says to do it for 3x6 BXT, and w/a db says both workarounds are for BXT until A0. Quite a nice mess. > > if (INTEL_REVID(dev) == BXT_REVID_A0) { > /* > -- > 1.9.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 093a5e4..c73d37d 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -124,12 +124,17 @@ static void bxt_init_clock_gating(struct drm_device *dev) I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | GEN8_SDEUNIT_CLOCK_GATE_DISABLE); - /* - * FIXME: - * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only. + /* WaSetHDCunitClckGatingDisable:bxt */ + /* WaSetHdcUnitClockGatingDisableInUcgctl6:bxt */ + /* The implementation is same for both of these WA except that + * WaSetHdcUnitClockGatingDisableInUcgctl6 is only applicable when + * either SS0 or SS2 is active but if we apply the first one then the + * second one also gets applied irrespective of which SS is enabled. */ - I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | - GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ); + if (INTEL_REVID(dev) == BXT_REVID_A0) { + I915_WRITE(GEN8_UCGCTL6, (I915_READ(GEN8_UCGCTL6) | + GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ)); + } if (INTEL_REVID(dev) == BXT_REVID_A0) { /*
The implementation for this WA is same as WaSetHdcUnitClockGatingDisableInUcgctl6. Both of them are for BXT:A0 except that WaSetHdcUnitClockGatingDisableInUcgctl6 is applicable only when either SS0 or SS2 is active but if we apply the former WA then the latter one also gets applied irrespective of which SS is enabled. Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com> --- drivers/gpu/drm/i915/intel_pm.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-)