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[RFC,19/22] drm/i915/slpc: Add parameter unset/set/get functions

Message ID 1453343184-160456-20-git-send-email-tom.orourke@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

tom.orourke@intel.com Jan. 21, 2016, 2:26 a.m. UTC 
From: Tom O'Rourke <Tom.O'Rourke@intel.com>

Add slcp_param_id enum values.
Add events for setting/unsetting parameters.

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
---
 drivers/gpu/drm/i915/intel_slpc.c | 127 ++++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_slpc.h |  22 +++++++
 2 files changed, 149 insertions(+)
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Patch

diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index 36aedb9..3abaf0b 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -119,6 +119,47 @@  static int host2guc_slpc_query_task_state(struct drm_i915_private *dev_priv)
 	return ret;
 }
 
+static int host2guc_slpc_set_param(struct drm_i915_private *dev_priv,
+				   enum slpc_param_id id, u32 value)
+{
+	u32 data[4];
+	int ret;
+
+	data[0] = HOST2GUC_ACTION_SLPC_REQUEST;
+	data[1] = SLPC_EVENT(SLPC_EVENT_PARAMETER_SET, 2);
+	data[2] = (u32) id;
+	data[3] = value;
+
+	ret = host2guc_action(&dev_priv->guc, data, 4);
+
+	if (0 == ret) {
+		ret = I915_READ(SOFT_SCRATCH(1));
+		ret &= 0xFF;
+	}
+
+	return ret;
+}
+
+static int host2guc_slpc_unset_param(struct drm_i915_private *dev_priv,
+				     enum slpc_param_id id)
+{
+	u32 data[3];
+	int ret;
+
+	data[0] = HOST2GUC_ACTION_SLPC_REQUEST;
+	data[1] = SLPC_EVENT(SLPC_EVENT_PARAMETER_UNSET, 1);
+	data[2] = (u32) id;
+
+	ret = host2guc_action(&dev_priv->guc, data, 3);
+
+	if (0 == ret) {
+		ret = I915_READ(SOFT_SCRATCH(1));
+		ret &= 0xFF;
+	}
+
+	return ret;
+}
+
 static u8 slpc_get_platform_sku(struct drm_i915_gem_object *obj)
 {
 	struct drm_device *dev = obj->base.dev;
@@ -370,3 +411,89 @@  int intel_slpc_query_task_state(struct drm_device *dev)
 
 	return host2guc_slpc_query_task_state(dev_priv);
 }
+
+int intel_slpc_unset_param(struct drm_device *dev, enum slpc_param_id id)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_i915_gem_object *obj;
+	struct page *page;
+	struct slpc_shared_data *data = NULL;
+	int ret = 0;
+
+	obj = dev_priv->guc.slpc.shared_data_obj;
+	if (obj) {
+		page = i915_gem_object_get_page(obj, 0);
+		if (page)
+			data = kmap_atomic(page);
+	}
+
+	if (data) {
+		data->override_parameters_set_bits[id >> 5]
+							&= (~(1 << (id % 32)));
+		data->override_parameters_values[id] = 0;
+		kunmap_atomic(data);
+
+		ret = host2guc_slpc_unset_param(dev_priv, id);
+	}
+
+	return ret;
+}
+
+int intel_slpc_set_param(struct drm_device *dev, enum slpc_param_id id,
+                         u32 value)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_i915_gem_object *obj;
+	struct page *page;
+	struct slpc_shared_data *data = NULL;
+	int ret = 0;
+
+	obj = dev_priv->guc.slpc.shared_data_obj;
+	if (obj) {
+		page = i915_gem_object_get_page(obj, 0);
+		if (page)
+			data = kmap_atomic(page);
+	}
+
+	if (data) {
+		data->override_parameters_set_bits[id >> 5]
+							|= (1 << (id % 32));
+		data->override_parameters_values[id] = value;
+		kunmap_atomic(data);
+
+		ret = host2guc_slpc_set_param(dev_priv, id, value);
+	}
+
+	return ret;
+}
+
+int intel_slpc_get_param(struct drm_device *dev, enum slpc_param_id id,
+                         int *overriding, u32 *value)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_i915_gem_object *obj;
+	struct page *page;
+	struct slpc_shared_data *data = NULL;
+	u32 bits;
+	int ret = 0;
+
+	obj = dev_priv->guc.slpc.shared_data_obj;
+	if (obj) {
+		page = i915_gem_object_get_page(obj, 0);
+		if (page)
+			data = kmap_atomic(page);
+	}
+
+	if (data) {
+		if (overriding) {
+			bits = data->override_parameters_set_bits[id >> 5];
+			*overriding = (0 != (bits & (1 << (id % 32))));
+		}
+		if (value)
+			*value = data->override_parameters_values[id];
+
+		kunmap_atomic(data);
+	}
+
+	return ret;
+}
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index 32d7dcc..fc74ce3 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -68,6 +68,23 @@  enum slpc_event_id {
 
 #define SLPC_EVENT(id, argc) ((u32) (id) << 8 | (argc))
 
+enum slpc_param_id {
+	SLPC_PARAM_TASK_ENABLE_DFPS = 2,
+	SLPC_PARAM_TASK_DISABLE_DFPS = 3,
+	SLPC_PARAM_TASK_ENABLE_TURBO = 4,
+	SLPC_PARAM_TASK_DISABLE_TURBO = 5,
+	SLPC_PARAM_TASK_ENABLE_DCC = 6,
+	SLPC_PARAM_TASK_DISABLE_DCC = 7,
+	SLPC_PARAM_GLOBAL_MIN_GT_FREQ_MHZ = 8,
+	SLPC_PARAM_GLOBAL_MAX_GT_FREQ_MHZ = 9,
+	SLPC_PARAM_DFPS_THRESHOLD_MAX_FPS = 10,
+	SLPC_PARAM_GLOBAL_DISABLE_GT_FREQ_MANAGEMENT = 11,
+	SLPC_PARAM_DFPS_DISABLE_FRAMERATE_STALLING = 12,
+	SLPC_PARAM_GLOBAL_DISABLE_RC6_MODE_CHANGE = 13,
+	SLPC_PARAM_GLOBAL_OC_UNSLICE_FREQ_MHZ = 14,
+	SLPC_PARAM_GLOBAL_OC_SLICE_FREQ_MHZ = 15,
+};
+
 enum slpc_global_state {
 	SLPC_GLOBAL_STATE_NOT_RUNNING = 0,
 	SLPC_GLOBAL_STATE_INITIALIZING = 1,
@@ -182,4 +199,9 @@  int intel_slpc_update_display_mode_info(struct drm_device *dev);
 int intel_slpc_update_display_rr_info(struct drm_device *dev, u32 refresh_rate);
 
 int intel_slpc_query_task_state(struct drm_device *dev);
+int intel_slpc_unset_param(struct drm_device *dev, enum slpc_param_id id);
+int intel_slpc_set_param(struct drm_device *dev, enum slpc_param_id id,
+			 u32 value);
+int intel_slpc_get_param(struct drm_device *dev, enum slpc_param_id id,
+			 int *overriding, u32 *value);
 #endif